2.5 Advanced Approaches for Reliability Improvement
Date:
Tue, 2009-04-21Time:
11:30 - 13:00Location / Room:
Erato, Level 3Moderators:
B Becker, Freiburg U, DE
M Psarakis, Piraeus U, GR
This session is about techniques for detecting and mitigating performance degradation due to aging effects for reliability improvement.
| 1130 | JOINT LOGIC RESTRUCTURING AND PIN REORDERING FOR MITIGATING NBTI-INDUCED EFFECTS K-C Wu and D Marculescu, Crnegie Mellon U, US |
| 1200 | A SELF-ADAPTIVE SYSTEM ARCHITECTURE TO ADDRESS TRANSISTOR AGING O Khan and S Kundu, U of Massachusetts, Amherst, US |
| 1230 | MASKING TIMING ERRORS ON SPEED-PATHS IN LOGIC CIRCUITS M R Choudhury and K Mohanram, Rice U, US |
