2.2 Emerging Interconnection Technologies for Multicore
Date:
Tue, 2009-04-21Time:
11:30 - 13:00Location / Room:
Clio, Level 3Moderators:
P Paulin, STMicroelectronics, FR
G Nicolescu, Polytechnique Montreal, CA
This session presents highly advanced techniques for NoC technologies and design tools. The first paper proposes an optical NoC in fat tree topology. The second paper presents a system-level synthesis tool for 3D NoC. The third paper suggests a novel technique to integrate user behaviour into the design flow. The final paper proposes a reconfigurable routing algorithm to boost fault resilience of NoC.
| 1130 | A LOW-POWER FAT TREE-BASED OPTICAL NETWORK-ON-CHIP FOR MULTIPROCESSOR SYSTEM-ON-CHIP H Gu and J Xu, Hong Kong U of Science and Technology, HK W Zhang, Princeton U, US |
| 1200 | A TOOL FOR APPLICATION SPECIFIC SYNTHESIS OF 3D NETWORKS ON CHIPS C Seiculescu, S Murali and G De Micheli, LSI, EPFL, Lausanne, CH L Benini, DEIS – Bologna U, IT |
| 1230 (S) | USER-CENTRIC DESIGN SPACE EXPLORATION FOR HETEROGENEOUS NETWORK-ON-CHIP PLATFORMS C-L Chou and R Marculescu, Carnegie Mellon U, US |
| 1245 (S) | A HIGHLY RESILIENT ROUTING ALGORITHM FOR FAULT-TOLERANT NoCs D Fick, A DeOrio, G Chen, V Bertacco, D Sylvester and D Blaauw, U of Michigan, US |
