Moderators:
M Fujita, Tokyo U, JP
V Kravets, IBM, US
This session covers advances in sequential logic analysis and optimisation as well as novel techniques for multi-cycle design. The first paper extends the notion of SPFD's to the sequential domain. The second paper provides an automated design framework for variable- latency implementations. The third paper provides accurate estimates of delay in multi- cycle paths.
| 1600 | SEQUENTIAL LOGIC RECTIFICATION WITH APPROXIMATE SPFDS Y-S Yang and A Veneris, Toronto U, CA S Sinha, Synopsys, US R K Brayton, UC Berkeley, US D Smith, Vennsa Technologies Inc, CA |
| 1630 | VARIABLE-LATENCY DESIGN BY FUNCTION SPECULATION D Baneres, U Oberta de Catalunya, ES J Cortadella, UP Catalunya, ES M Kishinevsky, Intel Corporation, US |
| 1700 | FIXED POINTS IN MULTI-CYCLE PATH DETECTION V D'Silva and D Kroening, Oxford U, UK |