11.7 Advances in Field Programmable Architectures and Applications
Date:
Thu, 2009-04-23Time:
14:00 - 15:30Location / Room:
Gallieni AB, Level 2Moderators:
P Lysaght, Xilinx, US
K Bertels, TU Delft, NL
The papers in this section present three different and complementary approaches to accelerating embedded and reconfigurable architectures.
| 1400 | EXPLOITING CLOCK SKEW SCHEDULING FOR FPGA S Bae, P Mangalagiri and V Narayanan, Pennsylvania State U, US |
| 1430 | ACCELERATING FPGA-BASED EMULATION OF QUASI-CYCLIC LDPC CODES WITH VECTOR PROCESSING X Chen, S Lin and V Akella, UC Davis, US |
| 1500 | RUNTIME RECONFIGURATION OF CUSTOM INSTRUCTIONS FOR REAL-TIME EMBEDDED SYSTEMS H P Huynh and T Mitra, National U of Singapore, SG |
