11.6 Automating Model Generation and Implementation
Date:
Thu, 2009-04-23Time:
14:00 - 15:30Location / Room:
Uranie, Level 3Moderators:
A Gerstlauer, U of Texas at Austin, US
D Borrione, TIMA Laboratory, FR
Automating the construction, implementation or optimisation of design models is the focus of this session. The first paper extracts a state machine model from simulation testbenches, and generates device drivers from it. The second paper addresses the optimisation of buffer sizes when scheduling synchronous data flow graphs on parallel architectures. The third contribution extends the hybrid finite state machine model to specify AMS behaviour. The session ends with an implementation of the discrete event specified system in SystemC.
| 1400 | CORRECT-BY-CONSTRUCTION GENERATION OF DEVICE DRIVERS BASED ON RTL TESTBENCHES N Bombieri, F Fummi, G Pravadelli and S Vinco, Verona U, IT |
| 1430 | BUFFER MINIMIZATION OF REAL-TIME STREAMING APPLICATIONS ON HYBRID CPU/FPGA J Zhu, I Sander and A Jantsch, Royal Institute of Technology, SE |
| 1500 (S) | A FORMAL APPROACH FOR SPECIFICATION-DRIVEN AMS BEHAVIORAL MODEL GENERATION S Mukherjee, A Ain, S K Panda, R Mukhopadhyay and P Dasgupta, Indian Institute Of Technology, Kharagpur, IN |
| 1515 (S) | SC-DEVS: AN EFFICIENT SYSTEMC EXTENSION FOR THE DEVS MODEL OF COMPUTATION F Madlener, H G Molter and S A Huss, TU Darmstadt, DE |
