11.2 High-Level Power and Thermal Management
Date:
Thu, 2009-04-23Time:
14:00 - 15:30Location / Room:
Clio, Level 3Moderators:
T Ishihara, Kyushu U, JP
B Mishra, Southampton U, UK
This section addresses several high-level power optimisation techniques, from variability compensation using adaptive supply voltage and body biasing to dynamic thermal-aware scheduling for 3D design, leakage-aware intra-task dynamic voltage/frequency scaling, and thermal-aware register file architecture.
| 1400 | EFFECTIVENESS OF ADAPTIVE SUPPLY VOLTAGE AND BODY BIAS AS POST-SILICON VARIABILITY COMPENSATION TECHNIQUES FOR FULL-SWING AND LOW-SWING ON-CHIP COMMUNICATION CHANNELS G Paci and L Benini, Bologna U, IT D Bertozzi, Ferrara U, IT |
| 1430 | DYNAMIC THERMAL MANAGEMENT IN 3D MULTICORE ARCHITECTURES A K Coskun and T Simunic-Rosing, UC San Diego, US D Atienza Alonso and J Leblebici, EPF Lausanne, CH J Ayala, Madrid Complutense U (UCM), ES |
| 1500 (S) | ENERGY MINIMIZATION FOR REAL-TIME SYSTEMS WITH NON-CONVEX AND DISCRETE OPERATION MODES F Dabiri, A Vahdatpour, M Potkonjak and M Sarrafzadeh, UCLA, US |
| 1515 (S) | EXPLOITING NARROW-WIDTH VALUES FOR THERMAL-AWARE REGISTER FILE DESIGNS S Wang, J Hu and S G Ziavras, New Jersey Institute of Technology, US S W Chung, Korea U, KR |
