The session deals with DFT solutions for memories and multiple-voltage designs, and with fault diagnosis in the context of output data compression.  The DFT technique presented in the first paper relies on word-line modulation to improve the testability of SRAM stability faults.  To reduce the number of voltage settings for testing multiple voltage designs, the second paper describes an algorithm for gate resizing.  Finally, the third paper tackles the problem of diagnosis using highly compressed output data, where test responses are compacted to a single parity bit.