10.4 Bursting Performance in Simulation and Debugging
Date:
Thu, 2009-04-23Time:
11:00 - 12:30Location / Room:
Thalie, Level 3 Moderators:
F Fummi, Verona U, IT
M Zwolinski, Southampton U, UK
The objectives of performance and accuracy are often mutually exclusive. The papers in this session look at resolving this dilemma. The first paper describes debugging techniques at gate level. Statistical static timing analysis of intra-chip variation is discussed in the second paper. The first short paper describes a method to speed up gate-level simulation using general purpose graphic processing units. The final paper proposes a method to deduce internal states of a system for debugging.
| 1100 | ON HIERARCHICAL STATISTICAL STATIC TIMING ANALYSIS B Li, N Chen, M Schmidt, W Schneider and U Schlichtmann, TU Munich, DE |
| 1130 | INCREASING THE ACCURACY OF SAT-BASED DEBUGGING A Suelflow, G Fey, U Kuehne and R Drechsler, Bremen U, DE C Braunsteine, Pierre & Marie Curie U, FR |
| 1200 (S) | GCS: HIGH-PERFORMANCE GATE-LEVEL SIMULATION WITH GP-GPUS D Chatterjee, A DeOrio and V Bertacco, U of Michigan, US |
| 1215 (S) | TRACE SIGNAL SELECTION FOR VISIBILITY ENHANCEMENT IN POST-SILICON VALIDATION X Liu and Q Xu, The Chinese U of Hong Kong, PRC |
