| A | System-Level Modelling, Analysis and Synthesis of Embedded Multi-Core Designs | 09:30 - 18:00 | Clio, Level 3 | Read More |
| B | Energy Harvesting Systems: Principles, Modelling and Performance Optimisation | 09:30 - 18:00 | Erato, Level 3 | Read More |
| C | Correct-by-Construction Embedded Software Synthesis: Formal Frameworks, Methodologies, and Tools | 09:30 - 18:00 | Room Thalie, Level 3 | Read More |
| D1 | New Developments and Trends in Networks on Chip | 09:30 - 13:00 | Gallieni AB, Level 2 | Read More |
| D2 | Formal and Semi-formal Methods for Correctness and Robustness | 14:30 - 18:00 | Gallieni AB, Level 2 | Read More |
| E1 | Low Power Design under Parameter Variations | 09:30 - 13:00 | Uranie, Level 3 | Read More |
| E2 | 3D Integration – Opportunities, Challenges and Industry Readiness - Perspectives from Design, Manufacturing and EDA | 14:30 - 18:00 | Uranie, Level 3 | Read More |
| F1 | Cross-Layer Approaches to Designing Reliable Systems using Unreliable Components | 09:30 - 13:00 | Gallieni 2, Level 2 | Read More |
| F2 | Power Optimised Design Techniques for Modern FPGAs | 14:30 - 18:00 | Gallieni 2, Level 2 | Read More |
| G1 | Advanced Testing and Test Driven Self-Tuning of Mixed-Signal/RF Circuits and Systems | 09:30 - 13:00 | Gallieni 3, Level 2 | Read More |
