DATE 2009

Monday-At-A-Glance

TUTORIALS

Organiser:
Alex Yakovlev, UK

Eleven pre-conference tutorials will be given on Monday.  Three are full-day tutorials (A, B, and C).  Eight are half-day tutorials, three to be given in the morning (D1, E1, F1, and G1) and three in the afternoon (D2, E2, F2, and G2).  A participant should enrol for either one full-day tutorial or two half-day tutorials (one in the morning and one in the afternoon).  For enrolment in half-day tutorials, you can choose any combination of the morning and afternoon half-day tutorials.  Combination of a full-day tutorial with a half-day tutorial is, however, not allowed. 

All tutorials run in parallel in accordance with the timetable below.

Rooms will be signposted.

0730 - 0930 Registration and Tutorial Breakfast (Agora 1 – opposite the registration desk)
0930 – 1100 Tutorials
1100 – 1130 Break
1130 – 1300 Tutorials
1300 – 1430 Lunch – (Les Muses – Level 3)
1330 CONFERENCE REGISTRATION BEGINS
1430 – 1600 Tutorials
1600 – 1630 Break
1630 – 1800 Tutorials
1800 – 1930 WELCOME RECEPTION (Agora 1 – in registration area)
1900 – 2100 FRINGE TECHNICAL MEETINGS
 

Track

Room

0930 - 1100

1130 - 1300

1430 - 1600

1630 - 1800

A

Clio, Level 3

System-Level Modelling, Analysis and Synthesis of Embedded Multi-Core Designs

cont.

cont.

cont.

B

Erato, Level 3

Energy Harvesting Systems: Principles, Modelling and Performance Optimisation

cont.

cont.

cont.

C

Thalie, Level 3

Correct-by-Construction Embedded Software Synthesis: Formal Frameworks, Methodologies, and Tools

cont.

cont.

cont.

D1/2

Gallieni AB, Level 2

New Developments and Trends in Networks on Chip

cont.

Formal and Semi-formal Methods for Correctness and Robustness

cont.

E1/2

Uranie, Level 3

Low Power Design under Parameter Variations

cont.

3D Integration – Opportunities, Challenges and Industry Readiness - Perspectives from Design, Manufacturing and EDA

cont.

F1/2

Gallieni 2, Level 2

Cross-Layer Approaches to Designing Reliable Systems using Unreliable Components

cont.

Power Optimized Design Techniques for Modern FPGAs

cont.

G1/2

Gallieni 3, Level 3

Advanced Testing and Test Driven Self-Tuning of Mixed-Signal/RF Circuits and Systems

cont.

Reliability, Availability and Serviceability of Networks-on-Chip

cont.