IP5 Interactive Presentations
Date:
Thu, 2009-04-23Time:
15:30 - 16:00Location / Room:
Exhibition Hall Rhodes, Level 2Each Interactive presentation will run on a ten minute rotation (three presentations per session) and will additionally be supported by a poster which will be on display throughout the afternoon.
| 1. | PERFORMANCE OPTIMAL SPEED CONTROL OF MULTI-CORE PROCESSORS UNDER THERMAL CONSTRAINTS V Hanumaiah, S Vrudhula and K Chatha, Arizona State U, US |
| 2. | SCALABLE COMPILE-TIME SCHEDULER FOR MULTI-CORE ARCHITECTURES M Pelcat, P Menuet and J-F Nezan, IETR/INSA, UMR CNRS 6164, Rennes, FR S Aridhi, Texas Instruments, FR |
| 3. | A HIERARCHICAL AND A GRADIENT ASCENT-BASED APPROACH TO PEAK POWER MANAGEMENT FOR MANY-CORE ARCHITECTURES J Sartori and R Kumar, Illinois, US |
| 4. | GENERATING THE TRACE QUALIFICATION CONFIGURATION FOR A MULTI-CORE DEBUG SYSTEM FROM A HIGH LEVEL LANGUAGE J Braunes, Pls Development Tools, DE R G Spallek, TU Dresden, DE |
| 5. | DYNAMIC AND DISTRIBUTED FREQUENCY ASSIGNMENT FOR ENERGY AND LATENCY CONSTRAINED MP-SoC D Puschini and F Clermidy, CEA Leti - MINATEC, FR P Benoit, G Sassatelli and L Torres, LIRMM, FR |
| 6. | A MILP-BASED APPROACH TO PATH SENSITIZATION OF EMBEDDED SOFTWARE C Costa and C Monteiro, TU Lisbon, IST / INESC-ID, PT |
| 7. | AN EFFICIENT AND DETERMINISTIC MULTITASKING RUN-TIME ENVIRONMENT FOR ADA AND THE RAVENSCAR PROFILE ON ATMEL AVR32 UC3A MICROCONTROLLER K Nyborg Gregertsen and A Skavhaug, NTNU, NO |
| 8. | TOWARD A RUNTIME SYSTEM FOR RECONFIGURABLE COMPUTERS: A VIRTUALIZATION APPROACH M Sabeghi and K Bertels, TU Delft, NL |
| 9. | SEPARATE COMPILATION AND EXECUTION OF IMPERATIVE SYNCHRONOUS MODULES E Vecchie and J-P Talpin, INRIA Rennes, FR K Schneider, Kaiserslautern U, DE |
