IP1 Interactive Presentations
Date:
Tue, 2009-04-21Time:
16:00 - 16:30Location / Room:
Exhibition Hall Rhodes, Level 2Each Interactive presentation will run on a ten minute rotation (three presentations per session) and will additionally be supported by a poster which will be on display throughout the afternoon.
| 1. | AN ACCURATE INTERCONNECT THERMAL MODEL USING EQUIVALENT TRANSMISSION LINE CIRCUIT B Wang and P Mazumder, U of Michigan, Ann Arbor, US |
| 2. | ANALOGUE MIXED SIGNAL SIMULATION USING SPICE AND SYSTEMC T Kirchner and N Bannow, Robert Bosch GmbH, DE C Grimm, TU Vienna, AT |
| 3. | RELIABILITY AWARE THROUGH SILICON VIA PLANNING FOR NANOSCALE 3D STACKED ICS A Shayan, M Popovich, X Chen, L Chua-Eoan and C Pan, Qualcomm Inc, US X Hu, H Peng and C-K Cheng, UC San Diego, US W Yu, Tsinghua U, PRC |
| 4. | A STUDY ON PLACEMENT OF POST SILICON CLOCK TUNING BUFFERS FOR MITIGATING IMPACT OF PROCESS VARIATION N Kelageri and S Kundu, U of Massachusetts, Amherst, US |
| 5. | ANALYSIS AND OPTIMIZATION OF NBTI INDUCED CLOCK SKEW IN GATED CLOCK TREES A Chakraborty, G V Ganesan, A Rajaram and D Z Pan, U of Texas at Austin, US |
| 6. | BITSTREAM RELOCATION WITH LOCAL CLOCK DOMAINS FOR PARTIALLY RECONFIGURABLE FPGAS A Flynn, A Gordon-Ross and A George, Florida U, US |
| 7. | PARALLEL TRANSISTOR LEVEL FULL-CHIP TRANSIENT CIRCUIT SIMULATION H Peng and C-K Cheng, UC San Diego, US |
| 8. | PERFORMANCE-DRIVEN DUAL-RAIL INSERTION FOR CHIP-LEVEL PRE-FABRICATED DESIGN F-W Chen and Y-Y Liu, Yuan Ze U, Taiwan, ROC |
| 9. | SIMULATION FRAMEWORK FOR EARLY PHASE EXPLORATION OF SDR PLATFORMS: A CASE STUDY OF PLATFORM DIMENSIONING M Trautmann and F Catthoor, KU Lueven and IMEC, BE S Mamagkakis, B Bougard, J Declerck, E Umans, A Dejonghe and L Van Der Perre, IMEC, BE |
| 10. | FAST AND ACCURATE PROTOCOL SPECIFIC BUS MODELING USING TLM 2.0 B Van Moll, TU Eindhoven, NL V Reyes, NXP Semiconductors, NL |
| 11. | INCORPORATING GRACEFUL DEGRADATION INTO EMBEDDED SYSTEM DESIGN M Glass, M Lukasiewycz and J Teich, Erlangen-Nuremberg, DE |
| 12. | REWIRING USING IRREDUNDANCY REMOVAL AND ADDITION C-C Lin and C-Y Wang, National Tsing Hua U, ROC |
