W3 Electronic System-Level Design towards Heterogeneous Computing

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Fri, 2014-03-28
Location / Room: 
Konferenz 3

Alessandro Cilardo, University of Naples Federico II, IT (Contact Alessandro Cilardo)
David Thomas, Imperial College, GB

Alessandro Cilardo is currently an assistant professor at the University of Naples Federico II, Italy. He is the single or main author of numerous peer-reviewed papers in leading scientific journals and conferences, such as IEEE Transactions on Computers, IEEE Transactions on Information Forensics Security, The Proceedings of the IEEE, DATE, FPL, ITC conferences, and others. His research activity focuses on highlevel, parallel programming paradigms for electronic system-level and FPGA design, including the automated translation of OpenMP-based multi-threaded programs to synthesizable HDL code. Other research topics include computer arithmetic, efficient implementation of cryptographic and security-related primitives, and HPC-based cryptanalysis.

David Thomas is a Lecturer in Electrical and Electronic Engineering at Imperial College, with a research interest in the acceleration of computationally intensive problems using technology such as GPUs and FPGAs. One area of focus is the development of tightly optimised libraries, such as random number generators for Monte Carlo, using new algorithms customised for the target architecture. Another topic of interest is the creation of high-level programming tools for heterogeneous platforms, allowing a single piece of source code to target multiple acceleration platforms.


Heterogeneous computing has emerged as a new important trend in computer architecture and high-performance computing. It refers to systems combining a variety of different computational units, such as general-purpose processors, special-purpose units, i.e. digital signal processors or the graphics processing units (GPUs), co-processors, custom accelerators, typically implemented on field-programmable gate arrays (FPGAs). The heterogeneous computing paradigm is rapidly extending its range to the development of complex embedded systems, multi-processor systems on chip and, in general, application-specific custom machines. The inclusion of FPGAs as heterogeneous accelerators for HPC platforms, furthermore, is introducing new challenges related to programmability, abstraction and programming paradigms, as well as new opportunities for hardware-accelerated high-performance and scientific computing applications. In fact, there are currently a large number of ongoing research projects and industrial initiatives centered on heterogeneous computing. The workshop will offer a global view of this rich and diverse research scenario. Representing the perspectives of both academia and industry, the talks will particularly address important cross-cutting issues involving system-level and embedded design in the light of the emerging heterogeneous computing trends.

Scope of the workshop and target audience

Heterogeneous computing involves a wide spectrum of research issues, such as programming paradigms, productivity, correctness, code optimization, processing and memory architectures. The workshop will cover all these aspects going from market trends to research issues and real-world applications. The talks will mostly have a tutorial nature and will put particular emphasis on opportunities for cross-fertilization. Touching a range of different research issues and perspectives, the workshop particularly targets researchers, industry experts, and students from many different areas, including:

  • electronic design automation;
  • computer architecture;
  • parallel programming, compilation, code optimization;
  • high-performance computing (HPC).

Call for Posters

A poster session will be organized during the workshop. Submission of posters is open to experts, researchers, PhD students working in any area across electronic system-level design and heterogeneous computing. The topics may include, but are not limited to, high-level synthesis, high-level programming paradigms, compilation, automated code parallelization and optimization, hybrid FPGA- and GPU-based platforms, interconnect and memory architectures for massively parallel heterogeneous platforms, and case-study applications. The research activities and use cases presented in the posters will be discussed interactively with the attendees. Authors should send a one-page short paper describing the contents of the poster to acilardo at unina [dot] it before February 16th 2014. The one-page short papers associated with posters will be included in the workshop digest.                                                      

Preliminary program

The preliminary program of the workshop is listed below. The talks will start from an industrial perspective, followed by an in-depth presentation of various research issues and opportunities as well as a presentation of real-world applications from the HPC domain. The talks will be divided in five sessions and will be interleaved with three panels and interactive discussions involving the audience.


08:30Opening Session
08:45Session 1 Trends in Heterogeneous Computing: the industrial perspective
08:45W3.2.1Heterogeneous Computing in the Cloud: emerging trends from the industry (Paper/SoftConf ID: 1276)
Steve Hebert, Nimbix,

09:15W3.2.2Higher Level Programming Abstractions for FPGAs using OpenCL (Paper/SoftConf ID: 1277)
Bogdan Pasca, Altera European Technology Centre,

09:45Panel 1
09:45W3.3.1Industry trends: bringing dedicated hardware acceleration to the market (Paper/SoftConf ID: 1302)
Koen Bertels1, Steve Hebert2 and Bogdan Pasca3
1Delft University of Technology, NL; 2Nimbix, ; 3Altera European Technology Centre,

10:30Coffee Break+Poster Session 1
11:00Session 2 - Research challenges in Heterogeneous Computing design flows
11:00W3.4.1FPGA based accelerators for Big Data: Polymorphic computing for Big Data (Paper/SoftConf ID: 1279)
Koen Bertels, Delft University of Technology,

11:30W3.4.2Mapping applications to heterogeneous accelerators: tool flows and run-time systems (Paper/SoftConf ID: 1280)
Christian Plessl, University of Paderborn,

13:00Session 3 -Compilers and code optimization for hardware-accelerated platforms
13:00W3.5.1From Software Code to Hardware: Directions in High-Level Synthesis (Paper/SoftConf ID: 1281)
Philippe Coussy, Université de Bretagne-Sud, Lab-STICC, FR

13:30W3.5.2Polyhedral compilation and code transformations for High-Level Synthesis (Paper/SoftConf ID: 1282)
Louis-Noel Pouchet, University of California Los Angeles, US

14:00Session 4 - Towards higher-level design approaches
14:00W3.6.1CoDesign with Verity: bidirectional control-flow across the FPGA-CPU divide (Paper/SoftConf ID: 1283)
Eduardo Aguilar Peleaz, Imperial College, GB

14:30W3.6.2Borrowing high-level paradigms from parallel computing: an OpenMP-based design flow (Paper/SoftConf ID: 1284)
Alessandro Cilardo, University of Naples Federico II, IT

15:00Panel 2
15:00W3.7.1ESL for Heterogeneous Computing: envisaging tomorrow’s tool flows (Paper/SoftConf ID: 1303)
Philippe Coussy1, Louis-Noel Pouchet2 and Eduardo Aguilar Peleaz3
1Université de Bretagne-Sud, Lab-STICC, FR; 2University of California Los Angeles, US; 3Imperial College, GB

15:30Coffee Break + Poster Session 2
16:00Session 5 - Current and emerging heterogeneous computing applications
16:00W3.8.1Heterogeneous HPC: combining FPGAs, CPUs, and GPUs for financial analytics (Paper/SoftConf ID: 1285)
David Thomas, Imperial College, GB

16:30Panel 3
16:30W3.9.1What role for dedicated hardware acceleration in tomorrow’s high-performance and scientific computing? (Paper/SoftConf ID: 1304)
Steve Hebert1 and Bogdan Pasca2
1Nimbix, ; 2Altera European Technology Centre,
Alessandro Cilardo3,

16:45Closing Session