M05 Test and diagnosis: Hierarchical Test for Today’s SOC and IoT

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Location / Room: 
Konferenz 5


Yervant Zorian, Synopsys, US (Contact Yervant Zorian)

Today’s SoC and IoT design teams, use heterogeneous IP blocks from numerous sources, and multi-level hierarchical architecture (IPs, cores, subchips, chip). To test such SOCs and IoTs, DFT designers adopt new hierarchical test solutions across heterogeneous cores (memories, logic, AMS and interface IP), in order to support concurrent test, power reductions during test, DFT closure, isolated debug and diagnosis, pattern porting, calibration, and uniform access. This tutorial covers hierarchical test trends and solutions based on IEEE test standards, such as IEEE 1500, 1687 and 1149.1, along with intelligent infrastructure IP to help achieve the above advantages.