W6 WORKSHOP: European SystemC User’s Group Workshop: OSCI and Accellera Core Technologies for the Next Generation of System-Level Design

Date: Friday 16 March, 2012
Time: 0830 - 1650
Location / Room: Konferenz 4

Organisers:
Axel Braun, European SystemC User’s Group/U Tuebingen, DE

The merger of the Open SystemC Initiative (OSCI) and Accellera to the Accellera Systems Initiative (ASI) unifies trend-setting standardization activities in the Electronic Design Automation (EDA) world and opens a wide range of new perspectives and synergies. The standards that are established and promoted by OSCI and Accellera cover a broad spectrum of today’s and tomorrow’s Electronic System Level (ESL) modeling and verification strategies.

This workshop is focused on the core technologies from both the OSCI and the Accellera world, and gives an outlook on how techniques may collaborate and converge. The format of the workshop includes four invited sessions from Doulos, Synopsys, Cadence, and VWorks providing a substantiated overview of the technologies and their future way-providing a practical guide on how those technologies can be successfully applied for improving a companies’ design strategy. Five user sections from XMOS, Sonics and Lantiq, the U Bremen, Bosch, and the Worcester Polytechnic Institute complement these core sections. They provide insights into the application and the development in research and industrial domains.

08:30	Welcome & Opening Wolfgang Rosenstiel, U Tuebingen & ESCUG, DE
08:40	Core Section 1: Doulos IEEE 1666-2011 SystemC Standard John Aynsley, Doulos, U.K.
09:40	User Section 1: Using SystemC with XMOS Devices David Lacey, XMOS, U.K.
10:10	Coffee Break
10:30	Core Section 2: Synopsys TLM-2.0 Technology for Off-Chip Interfaces Victor Reyes, Synopsys, US
11:30	User Section 2: SoC performance evaluation using high performance SystemQ and TLM models for communications SoCs Rocco Jonack, Sonics, US Bernhard Keppler, Lantiq, DE Renate Henftling, Lantiq, DE
12:00	Lunch Break
13:00	Core Section 3: Cadence Virtual Prototypes for Embedded Software Verification Markus Winterholer, Cadence, DE, Leonard Drucker, Cadence, US
14:00	User Section 3: SystemC-based ESL Verification Flow Integrating Property Checking and Automatic Debugging Hoang M. Le, Daniel Grosse, Rolf Drechsler, U Bremen and DFKI, DE
14:30	Coffee Break
14:50	Core Section 4: VWorks Programmable Debug of Linux/Android OS on Virtual PLatforms Jay Yantchev, VWorks, AU
15:50	User Section 4: Using IP-XACT to ease system development with SystemC/TLM The Transparent TLM (TTLM) Approach Simon Hufnagel, Bosch, DE, Christoph Grimm, Vienna U Technology, AT
16:20	User Section 5: System-Level Post-Manufacturing Testing Zainalabedin Navabi, Worcester Polytechnic Institute, US
16:50	Closing Wolfgang Rosenstiel, U Tuebingen & ESCUG, DE