IP5 INTERACTIVE PRESENTATIONS: Interactive Presentations

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Date: Thursday 15 March, 2012
Time: 1530 - 1600
Location / Room: Ground Floor

Each Interactive Presentation will run in a 30 minute presentation slot and will additionally be supported by a poster which will be on display throughout the afternoon. Additionally, each IP will be briefly introduced in a one-minute presentation in the relevant regular session.

No.IDPresentation Title
Authors
1IP5-1Session 10.5 - Thursday 1100-1230
EFFICIENT VARIATION-AWARE EM-SEMICONDUCTOR COUPLED SOLVER FOR THE TSV STRUCTURES IN 3D IC
Y Xu, L Jiang and N Wong, The U of Hong Kong, CN
W Yu, Tsinghua U, CN
Q Chen, UC San Diego, US
2IP5-2Session 10.5 - Thursday 1100-1230
VERIFYING JITTER IN AN ANALOG & MIXED SIGNAL DESIGN USING DYNAMIC TIME WARPING
R Narayanan, A Daghar, M H Zaki and S Tahar, Concordia U, CA
3IP5-3Session 10.6 - Thursday 1100-1230
MEDS: MOCKUP ELECTRONIC DATA SHEETS FOR AUTOMATED TESTING OF CYBER-PHYSICAL SYSTEMS USING DIGITAL MOCKUPS
B Miller and F Vahid, UC Riverside, US
T Givargis, UC Irvine, US
4IP5-4Session 10.6 - Thursday 1100-1230
COMPONENT-BASED AND ASPECT-ORIENTED METHODOLOGY AND TOOL FOR REAL-TIME EMBEDDED CONTROL SYSTEMS DESIGN
R Hamouche and R Kocik, Paris-Est U - ESIEE, FR
5IP5-5Session 10.6 - Thursday 1100-1230
CYBER-PHYSICAL CLOUD COMPUTING: THE BINDING AND MIGRATION PROBLEM
H Chen, R Hansen, J Huan, E Pereira, R Sengupta, R Swick and D Vizzini, UC Berkeley, US
C Kirsch, F Landolt, A Rottmann and R Trummer, Salzburg U, AT
6IP5-6Session 10.7 - Thursday 1100-1230
AN ADAPTIVE APPROACH FOR ONLINE HARD/SOFT FAULT MANAGEMENT IN MANY-CORE ARCHITECTURES
C Bolchini, A Miele and D Sciuto, Politecnico di Milano, IT
7IP5-7Session 10.7 - Thursday 1100-1230
AN HYBRID ARCHITECTURE TO DETECT TRANSIENT FAULTS IN MICROPROCESSORS: AN EXPERIMENTAL VALIDATION
S Campagna and M Violante, Politecnico di Torino - DAUIN, IT
8IP5-8Session 10.7 - Thursday 1100-1230
EVALUATION OF A NEW RFID SYSTEM PERFORMANCE MONITORING APPROACH
G Fritz, V Beroulle, O-E-K Aktouf and D Hély, Grenoble INP - LCIS, FR
9IP5-9Session 11.3 - Thursday 1400-1530
A FRAMEWORK FOR SIMULATING HYBRID MTJ/CMOS CIRCUITS: ATOMS TO CIRCUITS APPROACH
G Panagopoulos, C Augustine and K Roy, Purdue U, US
10IP5-10Session 11.3 - Thursday 1400-1530
A BLOCK-LEVEL FLASH MEMORY MANAGEMENT SCHEME FOR REDUCING WRITE ACTIVITIES IN PCM-BASED EMBEDDED SYSTEMS
D Liu, T Wang, Y Wang, Z Qin and Z Shao, The Hong Kong Polytechnic U, CN
11IP5-11Session 11.3 - Thursday 1400-1530
ARCHITECTING A COMMON-SOURCE-LINE ARRAY FOR BIPOLAR NON-VOLATILE MEMORY DEVICES
B Zhao, J Yang and Y Zhang, Pittsburgh U, US
Y Chen, Pittsburgh, US
H Li, Polytechnic Institute of NYU, ?
12IP5-12Session 11.3 - Thursday 1400-1530
LAYOUT-AWARE OPTIMIZATION OF TWO-TERMINAL STT MRAMS
S K Gupta, S P Park, N N Mojumder and K Roy, Purdue U, US
13IP5-13Session 11.4 - Thursday 1400-1530
CHARACTERIZATION OF THE BISTABLE RING PUF
Q Chen, P Lugli, U Schlichtmann and U Roehrmair, Munich TU, DE
G Csaba, Notre Dame U, US
14IP5-14Session 11.5 - Thursday 1400-1530
AN OPERATIONAL MATRIX-BASED ALGORITHM FOR SIMULATING LINEAR AND FRACTIONAL DIFFERENTIAL CIRCUITS
Y Wang, H Liu, G K H Pang and N Wong, The U of Hong Kong, CN
15IP5-15Session 11.6 - Thursday 1400-1530
A FLEXIBLE AND FAST SOFTWARE IMPLEMENTATION OF THE FFT ON THE BPE PLATFORM
T Cupaiuolo, STMicroelectronics, IT
D Lo Iacono, STMicroeletronics, IT
16IP5-16Session 11.7 - Thursday 1400-1530
HIERARCHICAL PROPAGATION OF GEOMETRIC CONSTRAINTS FOR FULL-CUSTOM PHYSICAL DESIGN OF ICS
M Mittag and G Jerke, Robert Bosch GmbH, DE
A Krinke, Dresden TU, DE
W Rosenstiel, Tuebingen U, DE
17IP5-17Session 11.7 - Thursday 1400-1530
DOUBLE-PATTERNING FRIENDLY GRID-BASED DETAILED ROUTING WITH ONLINE CONFLICT RESOLUTION
I S Abed, Mentor Graphics, EG
A G Wassal, Cairo U, EG
18IP5-18Session 11.7 - Thursday 1400-1530
DESIGN AND ANALYSIS OF VIA-CONFIGURABLE ROUTING FABRICS FOR STRUCTURED ASICS
H-P Tsai, L-C Lai and R-B Lin, Yuan Ze U, TW