G2 TUTORIAL: Testing Embedded Memories in the Nano-Era: Fault Models, Tests, Industrial Results and BIST

Date: Monday 12 March, 2012
Time: 1430 - 1800
Location / Room: Konferenz 6

Organisers:
Said Hamdioui, Delft U Technology, NL
Ad J. Van de Goor, Delft U Technology, NL

Speakers:
Said Hamdioui, Delft U Technology, NL
Ad J. Van de Goor, Delft U Technology, NL

The cost of memory testing increases with every generation of new memory chips. New technologies are introducing new defect mechanisms that were unknown in the past. Precise fault modeling to design efficient tests is therefore essential in order to keep the test cost and test time within economically acceptable limits, while keeping a high product quality.

The objective is to provide attendees with an overview of fault modeling, test design, BIST and BISR for memory devices in the nano-era. Traditional fault modeling and recent development in fault models for current and future technologies are covered. Systematic methods are presented for designing and optimizing tests, supported by industrial results from different companies (e.g. Intel, ST, Infineon) and for different technology nodes (e.g., 0.13um, 65nm). Impact of algorithmic (e.g., data-background) and non-algorithmic (e.g. voltage) stresses is explored in order to get better insight in the test effectiveness. State-of-the art and novel BIST architectures are covered; special attention is given to the optimization of address generator designs as they typically consume considerable BIST area overhead. BISR and redundancy analysis are also discussed. Finally, future challenges in memory testing are highlighted.

Target audience: Memory test engineers, memory and ASIC designers, production engineers, test researchers, managers involved in design and/or test of memories and SoCs.

Tutorial objectives: Upon the completion of the course, the attendee will have a good knowledge of practices in memory testing, understand the major types of memory faults and test, be able to develop new tests for any observed new faulty behaviors and optimize them, decide which memory BIST approach that has to be used based on the given design and constraints, etc.

Duration: Half day (3h)

SPEAKERS' BIOGRAPHIES

Said Hamdioui received the MSEE and PhD degrees (both with honors) from the Delft U Technology, Delft, The Netherlands. He is currently co-leading dependable-nano computing research activities within the Computer Engineering Laboratory of TUDelft. Prior to joining TUDelft, Hamdioui worked for Intel (Santa Clara, CA), Philips Semiconductors R&D (Crolles, France) and for Philips/ NXP Semiconductors (Nijmegen, the Netherlands). His research interests include dependable nano-computing and VLSI Design & Test (memory test, defect/fault tolerance, reliability, security, Design-for-Testability, Built-In-Self-Test, 3D stacked IC test, etc.) Hamdioui published one book and co-authored over 100 conference and journal papers. He consulted for many companies in the area of embedded memory testing. He is strongly involved in the international test technology community and he delivered dozens of keynote speeches, distinguished lectures, and invited presentations and tutorial at major international forums/conferences and at leading semiconductor companies. Hamdioui is the recipient of European Design Automation Association Outstanding Dissertation Award 2001, for his work on memory test techniques that have a wide-spread proliferation in the chip design industry; he is the winner of IEEE Nano and Nano Korea award at IEEE NANO 2010 - Joint Symposium with Nano Korea 2010; he was nominated for The Young Academy (DJA) of the Royal Netherlands Academy of Arts and Sciences (KNAW) in 2009, etc.

Ad J. van de Goor received the MSEE degree from the Delft U Technology, Delft, The Netherlands, in 1965, and the MSEE and PhD degrees from Carnegie Mellon U, Pittsburgh, Pennsylvania, in 1970. He worked with Digital Equipment Corp., Maynard, Masachusetts, as the chief architect of the PDP-11/45 computer. He also worked for IBM in The Netherlands and in the United States, being responsible for the architecture of embedded systems. He was a professor of computer engineering at the Delft U Technology and is currently emeritus professor at the same univeruty. He has written two books and more than 160 papers in the areas of computer architecture and testing. His main research interests are in testing memories and logic. Professor van de Goor is fellow of the IEEE.

Time	ID	Presentation Title Authors
1800		Break