F2 TUTORIAL: Design Methodology and Techniques in Production Low-Power SOC Designs

Date: Monday 12 March, 2012
Time: 1430 - 1800
Location / Room: Konferenz 5

Organisers:
Kaijian Shi, Cadence Design Systems, US

Speakers:
Kaijian Shi, Cadence Design Systems, US
Thomas Buechner, IBM, DE

Power has become a critical metric and key differentiator in sub-65nm SOC designs, due to growing power density driven by technology scaling and chip integration. This tutorial provides an overview of the low-power design methodologies and techniques in production SOC design perspective, emphasizing on the real design considerations and impact on chip success. We shall discuss pros and cons of the methods and techniques considering impacts on chip design schedule, yield, and overall power-performance target. We shall also discuss about design guidance and recommendations in various design steps and decision making points, based on our years of successful experience in production low-power SOC designs.

This tutorial is organized in two parts. In the first part, we shall overview power related challenges in sub-60nm SOC design and state-of-the-art techniques to reduce chip power. We shall give a holistic view from chip level to system and application levels. Practical industrial examples will be used to show how power savings can be achieved in modern SoC, processors and computer systems. In the second part, we shall describe production low-power design methodology and techniques particularly the power-gating and the voltage & frequency scaling which are the two advanced power reduction methods used effectively in sub-65nm production low-power designs. We shall explain when, where and how these methods and techniques are applied to a chip according to the design goals and time-to-market requirement. We shall also overview production low-power design methodology and flow with power intent descriptions.

Target audience: Engineers, project managers, academic researchers and students. We expect about 75 attendees who face challenges in production low-power SOC designs and demand for in-depth knowledge and industry proven design experience.

Tutorial objectives: At the end of the tutorials the attendees will have fundamental understanding of power saving techniques in modern SoC, processors and computer systems; production low-power design methodology and techniques particularly the power-gating and the voltage/frequency scaling; guidance on when, where and how these methods and techniques are applied to a chip according to the design goals and time-to-market requirement.

Duration: Half day (3h)

SPEAKERS' BIOGRAPHIES

Kaijian Shi is Solution Architect in Cadence Design Systems, specializing in low-power design methodology and implementation. He has worked as a consultant on more than 11 leading-edge commercial low-power designs all taped out successfully. Dr. Shi is one of the those in EDA and semiconductor industry who pioneer the low-power implementation methodology developments for production chip design. He has been a key contributor to the development of the advanced low-power production design flow in a leading semiconductor company which he has been consulting for. Dr. Shi co-authored the book “Low Power Methodology Manual for System-on-Chip Design” and has published 53 papers in journals and international conferences. He holds a Ph.D. degree from U Kent at Canterbury, UK since 1994. Dr. Shi is Technical Program co-Chair of the 25th IEEE SoC Conference in 2012. He was Chairman of IEEE Dallas Section in 2006 and Chairman of IEEE Circuits and System Society Dallas Chapter in 2004. He was Workshop chair and then publicity chair of IEEE SoC Conference 2008-2011 and program committee members of IEEE ISVLSI (2006-2008) and DesignCon since 2003.

Thomas Buechner is Advisory Engineer at IBM Research & Development Lab in Boeblingen, Germany, since 1994, where he is currently responsible for the design of power management units for IBM’s next generation POWERTM processors. Before that he has been involved in the development of many chips for high-end servers, from I/O hubs to complex SoCs. From 2007-2009 he led a workgroup to increase the power efficiency of server I/O hardware. He holds a Ph.D. degree from Stuttgart U since 1996. From 1989 to 1993 he was a Research Engineer at Institute for Microelectronics Stuttgart, Germany (IMS-Chips). He has published numerous papers at international conferences and holds several patents in the area of chip design and power reduction. Dr. Buechner has been actively involved in the organization of the IEEE ASIC, IEEE ASIC/SOC and IEEE SoC Conference (SOCC) since 1995, where he held several positions, including Program Chair, General Chair, and Steering Committee Chair. He acted as reviewer for numerous conferences including DAC, DATE, RAW, ASIC, ASIC-SOC, SOCC, DCIS, ReConFig and ISVLSI.

Time	ID	Presentation Title Authors
1800		Break