E2 TUTORIAL: The Device-to-System Spectrum – A Tutorial on IC Design with Nanomaterials

Date: Monday 12 March, 2012
Time: 1430 - 1800
Location / Room: Konferenz 4

Organisers:
Deming Chen, U Illinois at Urbana-Champaign, US
Subhasish Mitra, Stanford U, US

Speakers:
Deming Chen, U Illinois at Urbana-Champaign, US
Subhasish Mitra, Stanford U, US
Eric Pop, U Illinois at Urbana-Champaign, US
Naresh Shanbhag, U Illinois at Urbana-Champaign, US

Nanomaterials such as carbon nanotubes (CNT), graphene nanoribbons (GNR), nanowires (NW), and other emerging electronic elements, have the potential to revolutionize nanoelectronics by enabling favorable device properties, novel functionality, or ultra-low power operation. Nanomaterials have a significant potential for building superior devices, routing structures, and interconnects. These nanomaterials may be essential to sustaining the advancement of electronic systems or bringing in new functionality. Yet they are also facing unique challenges, such as higher defect rate and nanomaterial-specific process-related variations. Such unique challenges are more apparent for scaled CMOS technologies as well. Given the great promise of nanotechnolgy for the development of future electronics and the general interest of research on this fast-growing area, we gathered a group of experts to give a tutorial to share the vision, present the promises and challenges, inspire the audience, and enable further development of nanotechnology.

In this tutorial, we will first present the current state-of-the-art fabrication, modeling and operation of several new nanoscale device and circuit components. These will include design and fabrication of GNR transistors, CNT transistors, CNT logic, low-power phase-change memory, etc. While these innovations are fundamental for the establishment of nanotechnology, the true impact for electronic systems demands that we translate these device and component-level capabilities into system-level benefits. Therefore, the second focus of this tutorial strives to bridge the gap between nanoelectronic device research and nanosystems design. These include nanosystems prototype design and modeling, statistical design approaches, and error-resilient designs targeting high performance, high reliability, and low power. The ultimate goal is to expose the potential of nanoelectronic technology and the unique challenges it presents across the whole device-to-system spectrum. Tutorial presentations will encompass four segments, with the first two segments focusing on nanodevices and nanocomponents, and the last two segments on nanosystems and system-level optimizations on performance, power and reliability.

Target audience: What is the intended audience for this tutorial? how many? match with typical DATE audience?

Intended audience: would include both industrial and academic researchers. We expect that around 30 people would attend. The intended audience matches well with typical DATE audience.

Tutorial objectives: At the end of the tutorials the attendees will have fundamental understanding of the current state-of-the-art fabrication, modeling and operation of several new nanoscale device and circuit components, including design and fabrication of GNR transistors, CNT transistors, CNT logic, low-power phase-change memory, etc. The attendees will also learn about nanosystems prototype design and modeling, statistical design approaches, and error-resilient designs targeting high performance, high reliability, and low power. The ultimate goal is to expose the potential of nanoelectronic technology and the unique challenges it presents across the whole device-to-system spectrum.

Duration: Half day (3h)

SPEAKERS' BIOGRAPHIES

Deming Chen: Associate Professor, Electrical and Computer Engineering, U Illinois, Urbana-Champaign. Prof. Chen has focused on using NWs, CNTs and GNRs to design high density, high performance nanoFPGAs. His work includes 3D nanoFPGA designs, CNT and nanoswitch-based FPGA architectures, and graphene routing. His honors include several Best Paper Awards, NSF Career Award, and ACM Outstanding New Faculty Award. He is an IEEE Senior member and served as a TPC member in DAC, DATE, ICCAD, ASPDAC, FPGA, ISLPED, and ISQED. He is an associated editor for TCAS-I and TVLSI.

Subhasish Mitra: Associate Professor, Electrical Engineering and Computer Science, Stanford U. Prof. Mitra has co-authored more than 150 technical papers, and invented design and test techniques that have seen wide-spread proliferation in the semiconductor industry. His fabrication and design work on imperfection-immune circuits using CNTs has been highlighted by NSF, MIT Technology Review, EE Times, SRC, and several others. His honors include Presidential Early Career Award for Scientists and Engineers from the White House and several Best Paper Awards in leading conferences.

Eric Pop: Assistant Professor, Electrical and Computer Engineering, U Illinois, Urbana-Champaign. His research interests are in low-power nanoelectronics and nanoscale energy conversion systems. He obtained his Ph.D. in EE from Stanford (2005), the M.Eng./B.S. in EE and B.S. in Physics from MIT. His awards include the Presidential Early Career (PECASE) Award from the White House (2010) and Young Investigator Awards from the ONR, NSF, AFOSR (2010) and DARPA (2008). He is an IEEE Senior member and serves on the program committees of the DRC and IEDM conferences.

Naresh Shanbhag: Professor, Electrical and Computer Engineering, U Illinois, Urbana-Champaign. Prof. Shanbhag’s research interests are in the design of robust and energy-efficient integrated circuits and systems. He has authored more than 150 articles and holds eight US patents. His recent honors include 2010 Richard Newton GSRC Industrial Impact Award and IEEE Fellow in 2006. He also received several Best Paper Awards in leading journal and conferences. In 2000, Professor Shanbhag co-founded and served as the Chief Technology Officer of Intersymbol Communications, Inc. until it was acquired by Finisar Corp., Inc., in 2007.

Time	ID	Presentation Title Authors
1800		Break