The mounting issues of decreased yield and reliability from nanoscale IC processes require advanced approaches to the measurement and mitigation of device degradation and variance. Shrinking process geometries, with their corresponding reduction in device lifetimes, have broad implications to critical applications having long intended design lifetimes. Nanoscale transistor sizes are emerging as a major concern to the long term reliability of safety-critical systems in aerospace and automotive applications. Common semiconductor failure modes include Time Dependent Dielectric Breakdown (TDDB), hot carrier damage (HCI), and Negative Bias Temperature Instability (NBTI). Die-level prognostic test structures can detect and help mitigate the untimely failures in critical systems. These test structures, with variance measurement capabilities, also provide an effective platform for improved process-aware design for improved yields. This tutorial will address concepts of in-situ test structures as a solution to yield, reliability and prognostic applications and include practical application examples.

This tutorial is part of the annual IEEE Computer Society TTTC Test Technology Educational Program (TTEP)