This tutorial will review new 3D integration technologies and their impact on chip-package co-design.

In the morning, the tutorial will highlight the continuing needs for higher levels of integration and the mandates imposed by the stringent cost- and power constraints. The presenters will address the many benefits but also challenges 3D chip-stacking introduces and suggest methods to adopt the design of dies and advanced packages to higher levels of integration. In addition to new EDA tools and flows, our industry is adopting a new design practice: physical design prototyping of chip stacks. Several experts from industry and academia will share their experience and offer advice before the lunch break.

In the early afternoon session a representative from academia and two major EDA vendors will talk about the multi-physics challenges that need to be considered, both in new EDA flows and the physical design prototyping, to assure success.

Finally, two talks providing an outlook of how 3D technologies impact current and future products will summarise and end the day.