The increasing complexity of embedded systems has driven the development of new abstract modeling techniques, leading to the so-called Electronic System Level (ESL). For ESL design SystemC has become the de-facto system description language. In SystemC the most popular and widely used abstraction level is Transaction Level Modelling (TLM). Over the last years intensive research in academia and industry brought new methodologies and modelling standards such as OSCI TLM2 to today’s virtual prototype development. Virtual prototypes are used for many different tasks, as e.g. early SW development. As SW development based on virtual platforms is possible long before the silicon is available, the design productivity increases significantly.

However, to fully benefit from the productivity gain possible, the bottleneck of functional verification has to be addressed. Therefore, in the recent years different methodologies and approaches have been developed which target the verification of TLM designs and virtual prototypes. This tutorial outlines the verification challenges for SystemC models and in particular for ESL. Furthermore, different verification tasks are considered and the respective verification approaches are explained. It is shown to what level verification of TLM-models can be done with today’s verification methodologies and pros and cons of the approaches are discussed.