8.3 System Modelling for Design Space Exploration and Validation
Date:
Wed, 2010-03-10 Time:
17:00 - 18:30Location / Room:
Konferenz 1Moderators:
E Villar, Cantabria U, ES
L Indrusiak, York U, UK
Increasing system complexity widens the design space and dynamic reconfiguration possibilities for embedded systems. The papers in this session present various modelling strategies to constrain and simplify the design space exploration and validate the solutions, in particular with applications to dataflow systems and wireless sensor networks.
| 1700 | PARETO EFFICIENT DESIGN FOR RECONFIGURABLE STREAMING APPLICATIONS ON CPU/FPGAS J Zhu, I Sander and A Jantsch, Royal Institute of Technology, SE |
| 1730 | AUTOMATED BOTTLENECK-DRIVEN DESIGN-SPACE EXPLORATION OF MEDIA PROCESSING SYSTEM Y Yang, M Geilen, T Basten, S Stuijk and H Corporaal, TU Eindhoven, NL |
| 1800 | USING TRANSACTION LEVEL MODELING TECHNIQUES FOR WIRELESS SENSOR NETWORK SIMULATION M Damm, J Moreno, J Haase and C Grimm, TU Vienna, AT |
| 1815 | RTOS-AWARE REFINEMENT FOR TLM2.0-BASED HW/SW DESIGNS M Becker, T Xie and W Mueller, Paderborn U / C-LAB, DE G Di Guglielmo, G Pravadelli and F Fummi, Verona U, IT |
| IPs | IP4-1 |
| 1830 | CLOSE |
