7.8 PANEL SESSION - Who is closing the Embedded Software Design Gap?
Organiser:
G Martin, Tensilica, US
Moderator:
W Ecker, Infineon, DE
Panellists:
Pierre Bricaud, Synopsys, FR
Rainer Doemer, UC Irvine, US
Yossi Veller, Mentor Graphics, US
Stefan Heinen, Infineon, DE
Jürgen Mössinger, Bosch, DE
Andreas von Schwerin, Siemens, DE
As pointed out in the ITRS roadmap, the level of embedded software complexity is greater than the pure HW complexity of SoCs when comparing, for example, lines of HDL and C code. Even worse, SW complexity grows faster than HW complexity (Moore’s Law) and SW productivity increases more slowly than HW productivity. A new design gap - the gap of embedded software – has appeared.
EDA has now identified ESL as a field with sufficient revenue and revenue growth, but do they really approach the SW productivity challenge?
This panel gives the answer by presenting recent EDS products and solutions in the area of ESW, contrasting them with needs of industry, and discussing ways out of the ESL productivity crisis.
