5.3 Power Optimisation and Estimation for Flash and CMOS Technologies
Date:
Wed, 2010-03-10Time:
08:30 - 10:00Location / Room:
Konferenz 1Moderators:
J Chen, ETH Zurich, CH
M Poncino, Politecnico di Torino, IT
This session first presents a power estimation framework for flash memories; the remaining papers deal with static and dynamic power optimisation for digital CMOS designs, and low-power design methodologies for analogue primitives.
| 0830 | FLASHPOWER: A DETAILED POWER MODEL FOR NAND FLASH MEMORY V Mohan, S Gurumurthi and M R Stan, Virginia U, US |
| 0900 | POWER OPTIMIZATION DESIGN IN CMOS OP-AMPS WITH SUB-SPACE BASED GEOMETRIC PROGRAMMING W Gao, York U, Toronto, CA |
| 0930 | POWER GATING DESIGN FOR STANDARD-CELL-LIKE STRUCTURED ASICS S-Y Chen, R-B Lin, H-H Tung and K-W Lin, Yuan Ze U, Taiwan, ROC |
| 0945 | DUAL-VTH LEAKAGE REDUCTION WITH FAST CLOCK SKEW SCHEDULING ENHANCEMENT M Tie, H Dong, T Wang and X Cheng, Peking U, PRC |
| IPs | IP2-10, IP2-11 |
| 1000 | EXHIBITION BREAK/IP2 |
