5.2 Automating Verification with Simulation, Properties and Assertions
Date:
Wed, 2010-03-10Time:
08:30 - 10:00Location / Room:
Konferenz 6Organiser/Moderator:
V Bertacco, U of Michigan, US
M Lajolo, NEC Labs, US
The session is centered on fast and automatic solutions in functional validation and verification. The first presentation evaluates the quality of user-defined functional properties. The second work is a semi-formal solution for microprocessor verification. The following contribution improves SAT-based bounded model checking in verifying a pool of properties. The last paper provides a fast cache simulation technique.
| 0830 | VACUITY ANALYSIS FOR PROPERTY QUALIFICATION BY MUTATION OF CHECKERS L Di Guglielmo, F Fummi and G Pravadelli, Verona U, IT |
| 0900 | AN ABSTRACTION-GUIDED SIMULATION APPROACH USING MARKOV MODELS FOR MICROPROCESSOR VERIFICATION T Zhang, T Lv, X-W Li, Chinese Academy of Sciences, PRC |
| 0930 | EFFICIENT DECISION ORDERING TECHNIQUES FOR SAT-BASED TEST GENERATION M Chen, X Qin and P Mishra, Florida U, US |
| 0945 | DEW: A FAST LEVEL 1 CACHE SIMULATION APPROACH FOR FIFO REPLACEMENT POLICY M Shihabul Haque, J Peddersen, A Janapsatya and S Parameswaran, New South Wales U, AU |
| IPs | IP2-8, IP2-9 |
| 1000 | EXHIBITION BREAK/IP2 |
