4.5 Wearout and Process Variation Mitigation and Modelling
Date:
Tue, 2010-03-09 Time:
17:00 - 18:30Location / Room:
Konferenz 3Moderators:
S Kundu, Massachusetts U, US
A El-Maleh, U of Petroleum and Minerals, CTRY???
The first paper in this session discusses an effective technique that extends the MTTF by exploiting the idle time of functional units in microprocessors. The second paper presents new technique for predicting circuits propagation delay in the presence of process variation. The third paper discusses an accurate analytical model to predict the delay of combinational gates subject TDDB, and the last paper presents static and dynamic stability improvements to SRAMS that minimise the impact of process variation.
| 1700 | PROACTIVE NBTI MITIGATION FOR BUSY FUNCTIONAL UNITS IN OUT-OF-ORDER MICROPROCESSORS L Li, Y Zhang and J Yang, Pittsburgh U, US J Zhao, Nanjing U, JP |
| 1730 | CIRCUIT PROPAGATION DELAY ESTIMATION THROUGH MULTIVARIATE REGRESSION-BASED MODELING UNDER SPATIO-TEMPORAL VARIABILITY S Ganapathy, R Canal and A Rubio, UP Catalunya, ES A Gonzalez, UP Catalunya and Intel Barcelona Research Center, ES |
| 1800 | ACCURATE ANALYTICAL MODEL FOR PERFORMANCE DEGRADATION DUE TO GATE OXIDE BREAKDOWN IN COMBINATIONAL LOGIC M Choudhury and K Mohanram, Rice U, US V Chandra and R Aitken, ARM, US |
| 1815 | STATIC AND DYNAMIC STABILITY IMPROVEMENT STRATEGIES FOR 6T CMOS LOW-POWER SRAMS B Alorda, G Torrens, S Bota and J Segura, Illes Balears U, ES |
| IPs | IP2-6 |
| 1830 | CLOSE |
