4.4 Application of Reconfigurable and Adaptive Systems
Date:
Tue, 2010-03-09Time:
17:00 - 18:30Location / Room:
Konferenz 2 Moderator:
C Heer, Infineon Technologies AG, DE
M Huebner, Karlsruhe U, DE
Starting from packet classification in NoC the session covers innovative memory and motion estimation architectures and concludes with a novel FPGA application in bio-chemistry.
| 1700 | A RAPID PROTOTYPING SYSTEM FOR ERROR-RESILIENT MULTI-PROCESSOR SYSTEMS-ON-CHIP M May and N Wehn, Kaiserslautern U, DE A Bouajila, J Zeppenfeld, W Stechele and A Herkersdorf, TU Munich, DE D Ziener and J Teich, Erlangen-Nuremberg U, DE |
| 1715 | LEARNING-BASED ADAPTATION TO APPLICATIONS AND ENVIRONMENTS IN A RECONFIGURABLE NETWORK-ON-CHIP J-S Shen, C-H Huang and P-A Hsiung, National Chung Cheng U, ROC |
| 1730 | APPLICATION-SPECIFIC MEMORY PERFORMANCE OF A HETEROGENEOUS RECONFIGURABLE ARCHITECTURE S Whitty, B Hurlburt, H Sahlbach and R Ernst, TU Braunschweig, DE W Putzke-Roeming, Deutsche Thomson OHG, DE |
| 1745 | A RECONFIGURABLE HARDWARE FOR ONE BIT TRANSFORM BASED MULTIPLE REFERENCE FRAME MOTION ESTIMATION A Akin, G Sayilar and I Hamzaoglu, Sabanci U, TK |
| 1800 | ULTRA-HIGH THROUGHPUT STRING MATCHING FOR DEEP PACKET INSPECTION A Kennedy, X Wang and Z Liu, Dublin City U, IE B Liu, Tsinghua U, PRC |
| 1815 | A HMMER HARDWARE ACCELERATOR USING DIVERGENCES J F Eusse Giraldo, R Pezzuol Jacobi and A C Magalhaes Alves De Melo, Brasilia U, BR N Moreano, Federal U of Mato Grosso Do Sul, BR |
| IPs | IP2-4, IP2-5 |
| 1830 | CLOSE |
