4.2 Variability Aware Low Power Design
Date:
Tue, 2010-03-09 Time:
17:00 - 18:30Location / Room:
Konferenz 6 Moderators:
M Miranda, IMEC, BE
T Ishihara, Kyushu U, JP
This session presents novel low power circuit, architecture and system level design techniques for technology scaling induced problems. Challenging power critical components in todays SoCs are used as drivers such as FPGA, memories and power delivering networks.
| 1700 |
AVGS-MUX STYLE: A NOVEL TECHNOLOGY AND DEVICE INDEPENDENT TECHNIQUE FOR REDUCING POWER AND COMPENSATING PROCESS VARIATIONS IN FPGA FABRICS B Kheradmand-Boroujeni and C Piguet, CSEM, CH Y Leblebici, EPF Lausanne, CH |
| 1730 |
ON THE EFFICACY OF WRITE-ASSIST TECHNIQUES IN LOW VOLTAGE NANOSCALE SRAMS V Chandra, C Pietrzyk and R Aitken, ARM, US |
| 1800 |
OPTIMIZING THE POWER DELIVERY NETWORK IN DYNAMICALLY VOLTAGE SCALED SYSTEMS WITH UNCERTAIN POWER MODE TRANSITION TIMES H Jung and M Pedram, Southern California U, US |
| IPs | IP2-1, IP2-2 |
| 1830 | CLOSE |
