Organisers:
Yervant Zorian, Virage Logic, US
Moderator:
Peggy Aycinena, EDA Weekly, US
Executives:
C J Clark, CEO & President, Intellitech, US
Pierre Garnier, Vice President & GM, Texas Instruments, FR
Subi Kengeri, Vice President, Global Foundries, US
Joe Macri, Vice President & CTO, AMD, US
Joe Sawiki, VP & GM, Mentor Graphics, US
Naveed Sherwani, President & CEO, Open Silicon, US
Today's nanometer semiconductor fabrication processes result in susceptibility levels that negatively impact process manufacturability and yield, and hence lengthen the SoC production ramp-up period, and affect profitability. To optimise manufacturability and reach acceptable yield levels, the industry needs advanced optimisation solutions. The executives in session will discuss such solutions and their economic impact.
| 1600 | BREAK/IP1 |