2.5 Reliability, Simulation, Yield and Enhancement
Date:
Tue, 2010-03-09 Time:
11:30 - 13:00Location / Room:
Konferenz 3 Moderators:
R Aitken, ARM, US
V Singh, Indian Institute of Science (IISc), IN
This session covers some of the recent advances in reliable designs and chip yield improvements. The first paper presents a system level simulation framework to evaluate lifetime SoC reliability. The second and third papers discuss novel yield enhancements techniques. The last paper presents a methodology for improving the reliability of power gated designs.
| 1130 | AGESIM: A SIMULATION FRAMEWORK FOR EVALUATING THE LIFETIME RELIABILITY OF PROCESSOR-BASED SoCs L Huang and Q Xu, The Chinese U of Hong Kong, PRC |
| 1200 | STATISTICAL SRAM ANALYSIS FOR YIELD ENHANCEMENT P Zuber, M Miranda, P Dobrovolny and K van der Zanden, IMEC, SSET/DC, BE J Jung, System LSI Division, Samsung Electronics Co., KR |
| 1230 | COST-EFFECTIVE IR-DROP FAILURE IDENTIFICATION AND YIELD RECOVERY THROUGH A FAILURE-ADAPTIVE TEST SCHEME M Chen and A Orialoglu, UC San Diego, US |
| 1245 | SCAN BASED METHODOLOGY FOR RELIABLE STATE RETENTION POWER GATING DESIGNS S Yang, B Al-Hashimi and S Khursheed, Southampton U, UK D Flynn, ARM, Cambridge, UK |
| IPs | IP1-4, IP1-5 |
| 1300 | LUNCH BREAK |
