2.4 System Level Design of Multicores

Date:

Tue, 2010-03-09

Time:

11:30 - 13:00

Location / Room:

Konferenz 2

Moderators:
V Zaccaria, Politecnico di Milano, IT
M Coppola, STMicroelectronics, FR

The session covers the design of NoC-based multicore architectures with emphasis on reliability, low-power and high performance.

1130	MULTICORE SOFT ERROR RATE STABILIZATION USING ADAPTIVE DUAL MODULAR REDUNDANCY R Vadlamani, J Zhao, W Burleson and R Tessier, U of Massachusetts, Amherst, US
1200	A FULLY-ASYNCHRONOUS LOW-POWER FRAMEWORK FOR GALS NoC INTEGRATION Y Thonnart, P Vivet and F Clermidy, CEA-LETI, MINATEC, FR
1230	SUPPORTING DISTRIBUTED SHARED MEMORY ON MULTI-CORE NETWORK-ON-CHIPS USING A DUAL MICROCODED CONTROLLER X Chen, Z Lu and A Jantsch, Royal Institute of Technology (KTH), SE S Chen, National U of Defense Technology, PRC
1245	MEDEA: A HYBRID SHARED-MEMORY/MESSAGE-PASSING MULTIPROCESSOR NoC-BASED ARCHITECTURE S V Tota, M R Casu, M Ruo Roch, L Rostagno and M Zamboni, Politecnico di Torino, IT
IPs	IP1-3
1300	LUNCH BREAK

DATE Area