IP1 Interactive Presentations
Date:
Tue, 2010-03-09 Time:
16:00 - 16:30Location / Room:
Exhibition Area, Ground FloorEach Interactive presentation will run on a ten minute rotation (three presentations per session) and will additionally be supported by a poster which will be on display throughout the afternoon. Additionally, each IP will be briefly introduced in a one-minute presentation in the relevant regular session.
| IP1-1 | HIGH-FIDELITY MARKOVIAN POWER MODEL FOR PROTOCOLS J Cao and A Nymeyer, New South Wales U, AU |
| IP1-2 | ENERGY-PERFORMANCE DESIGN SPACE EXPLORATION OF SMT ARCHITECTURES EXPLOITING SELECTIVE LOAD VALUE PREDICTIONS A Gellert, A Florea and L Vintan, Sibiu U, RO G Palermo, V Zaccaria and C Silvano, Politecnico di Milano, IT |
| IP1-3 | ERROR RESILIENCE OF INTRA-DIE AND INTER-DIE COMMUNICATION WITH 3D SPIDERGON STNoC V Pasca, L Anghel and C Rusu, TIMA Laboratories, FR R Locatelli and M Coppola, STMicroelectronics, FR |
| IP1-4 | TOWARDS A CHIP LEVEL RELIABILITY SIMULATOR FOR COPPER/LOW-K BACKEND PROCESSES M M Bashir and L Milor, Georgia Institute of Technology, US |
| IP1-5 | NBTI MODELING IN THE FRAMEWORK OF TEMPERATURE VARIATION S Khan and S Hamdioui, TU Delft, NL |
| IP1-6 | RUNASSERT: A NON-INTRUSIVE RUN-TIME ASSERTION FOR PARALLEL PROGRAMS DEBUGGING C-N Wen, S-H Chou and T-F Chen, National Chung Cheng U, ROC T-J Lin, ITRI STC, ROC |
| IP1-7 | AN RDL-CONFIGURABLE 3D MEMORY TIER TO REPLACE ON-CHIP SRAM M Facchini, IMEC and KU Leuven, BE D Velenis and P Marchal, IMEC, BE W Dehaene, KU Leuven, BE |
| IP1-8 | GENTLECOOL: COOLING AWARE PROACTIVE WORKLOAD SCHEDULING IN MULTI-MACHINE SYSTEMS R Ayoub, S Sharifi and T Rosing, UC San Diego, US |
| IP1-9 | TIMING MODELING FOR DIGITAL SUB-THRESHOLD CIRCUITS N Lotze, J Goeppert and Y Manoli, Freiburg U - IMTEK, DE |
| IP1-10 | POWER CONSUMPTION OF LOGIC CIRCUITS IN AMBIPOLAR CARBON NANOTUBE TECHNOLOGY M H Ben-Jamaa and G De Micheli, EPF Lausanne, CH K Mohanram, Rice U, US |
| IP1-11 | REVERSIBLE LOGIC SYNTHESIS THROUGH ANT COLONY OPTIMIZATION M Li, Y Zheng, M S Hsiao and C Huang, Virginia Tech, US |
| IP1-12 | LOW -POWER FINFET CIRCUIT SYNTHESIS USING SURFACE ORIENTATION OPTIMIZATION P Mishra and N K Jha, Princeton U, US |
| IP1-13 | IMPLEMENTING DIGITAL LOGIC WITH SINUSOIDAL SUPPLIES K C Bollapalli, S P Khatri and L Kish, Texas A&M U, US |
| IP1-14 | A RECONFIGURABLE MULTIPROCESSOR ARCHITECTURE FOR A RELIABLE FACE RECOGNITION IMPLEMENTATION A Tumeo, G Palermo, F Ferrandi and D Sciuto, Politecnico di Milano, IT F Regazzoni, Alari, IT |
| IP1-15 | A SYSTEMATIC APPROACH TO COMBINED HW/SW SYSTEM TEST A Krupp, W Mueller and A Elfeky, Paderborn U/C-LAB, DE |
| IP1-16 | A NEW APPROACH FOR ADAPTIVE FAILURE DIAGNOSTICS BASED ON EMULATION TEST S Ostendorff, J Sachsse and H-D Wuttke, TU lmenau, DE S Koehler, Goepel Electronic GmbH, DE |
| IP1-17 | INTEGRATED END-TO-END TIMING ANALYSIS OF INTEGRATED END-TO-END TIMING ANALYSIS OF NETWORKED AUTOSAR-COMPLIANT SYSTEMS K Lakshmanan, G Bhatia and R Rajkumar, Carnegie Mellon U, US |
| IP1-18 | SCALABLE STOCHASTIC PROCESSORS S Narayanan, J Sartori, R Kumar and D L Jones, U of Illinois at Urbana Champaign, US |
