W5 3D Integration – Technology, Architecture, Design, Automation and Test
Please visit the homepage of 3D Integration Workshop 2010.
Organisers:
Erik Jan Marinissen, IMEC, BE
Yann Guillou, ST-Ericsson, FR
Geert Van der Plas, IMEC, BE
Please find here the Call for Paper as PDF.
Please find here the Electronic Workshop Digest (~ 40 MB, Update: 4th May 2009)
Description:
3D Integration is a promising technology for extending Moore’s momentum in the next decennium, offering higher transistor density, faster interconnects, heterogeneous technology integration, and potentially lower cost and time-to-market. But before 3D chips can be produced, new capabilities are needed: process technology, architectures, design methods and tools, and manufacturing test solutions. The goal of this Workshop is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges.
The workshop program contains the following elements.
- A keynote address: "The Promise of Through-Silicon Vias" by Sitaram Arkalgud (Sematech, US)
- An invited talk: “Requirements for Design-for-3D Environment” by Riko Radojcic (Qualcomm, US)
- Two sessions with in total six regular presentations
- Two poster sessions
- A panel session discussing “The Future of 3D Integration from All Angles”
| 0830 | Moderator: Lisa McIlrath - R3Logic, US
SESSION 1 The Promise of Through-Silicon Vias 0930 Invited Talk: Abstract: The twin drivers of all advances in the semiconductor industry have been ever increasing performance and productivity. With tremendous strides in lithography and device development over the last several decades, achieving both has been possible. However, with fundamental issues and cost concerns surrounding new technology elements at 32nm and below the viability of traditional lithography and device scaling to stay on the productivity curve becomes questionable. One of the technologies gaining popularity has been Through-Silicon Vias (TSVs) for stacking chips in the third dimension. This presentation will discuss the merits of 3D TSVs, state of the art on 3D, the risks and challenges involved, the timeline, the need for understanding the cost implications and manufacturability, and the necessity for standardisation and classification. Qualcomm’s roadmap for 3D technology is outlined, and the corresponding requirements for a holistic design environment necessary to define and implement optimized 3D products are described. The focus is on the design environment and EDA tools necessary for ‘Stage 1’ class of products, consisting of a functionally partitioned two-die stack. The design environment requirements are segregated into three classes of methodologies and the associated EDA technologies. (a) “TechTuning” technologies required to co-optimize process technology and chip design requirements, and to define and validate the design rules and models required for 3D Design Authoring, |
| 1000 | POSTER SESSION 1 22 Posters - coffee + tea break |
| 1030 | Moderator: Peter Schneider, Fraunhofer Institute, DE
SESSION 2 |
| 1200 | LUNCHEON BREAK |
| 1300 | Moderator: Yuan Xie - Pennsylvania State University, US
SESSION 3 |
| 1430 | POSTER SESSION 2 22 Posters - coffee + tea break |
| 1500 | PANEL SESSION
“The Future of 3D Integration From All Angles” |
| 1600 | CLOSURE |
Poster Session 1 & 2
- 3D Technologies and Data Structures – An Overview,
Robert Fischbach, Jens Lienig – Dresden University of Technology, DE - System-Level Exploration of 3D Interconnection Schemes,
Kostas Siozios, A. Papanikolaou, Alexandros Bartzas, Dimitrios Soudris – National Technical University of Athens, GR - 3D Integrated Smart Antenna Systems,
Nakul Haridas, Tughrul Arslan – University of Edinburgh, UK - 3D Integration Program Overview,
Laurent Bonnot, Pascal Ancey, Damien Riquet, Pascal Urard – ST Microelectronics, FR; David Henry, Astrid Astier – CEA Léti, FR - Topology Exploration and Buffer Sizing for 3D Networks-on-Chip,
Alexandros Bartzas, Kostas Siozios, Dimitrios Soudris – National Technical University of Athens, GR - Closed-Form Equations for Through-Silicon Via Parasitics in 3D ICs,
Roshan Weerasekera, Dinesh Pamunuwa, Matt Grange – Lancaster University, UK; Hannu Tenhunen, Li-Rong Zheng – KTH, SE - 3D-NOCs, TSVs, Asynchronous Circuits, and Serial Vertical Links,
A. Sheibanyrad, F. Pétrot – TIMA/SLS, FR - Modular Modeling of RF Behavior of Interconnect Structures in 3D Integration,
Jörn Stolle, Sven Reitz, Peter Schneider, Andreas Wilde – Fraunhofer Institute for Integrated Circuits, DE - Evaluating Noise Coupling Issues in Mixed-Signal 3D ICs,
Liuchun Cai, Ramesh Harjani – University of Minnesota, US - Design, Verification and Simulation of 3D Circuit,
Guruprasad Katti, Bart De Wachter, Marc Nelis, Morin Dehan, Miroslav Cupak, Kris Croes, Gerd Beeckman, Pol Marchal, Michele Stucchi – IMEC, BE; Wim Dehaene – Katholieke Universiteit Leuven, BE - Examination of Delay and Signal Integrity Metrics in TSVs,
Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa – Lancaster University, UK; Hannu Tenhunen – KTH, SE - On-Chip Waveform Capturing Functionality Partitioned for 3D Realization,
Yuuki Araga, Yoji Bando, Takushi Hashida, Makoto Nagata – Kobe University, JP - Thermal Aware Test Scheduling for Stacked Multi-Chip Modules,
Vinay N.S., Virendra Singh – Indian Institute of Science, IN; Erik Larsson – Linköping University, SE - A Prospective Analysis of High-Frequency Cross-Coupling Mechanisms for the Next 3D Packaging Generation,
Roberto Antonicelli – ST-Ericsson, BE - Power Integrity Issues in 3D ICs using TSVs,
Waqar Ahamd, Qiang Chen, Roshan Weerasekera, Hannu Tenhunen, Lirong Zheng – KTH, SE - Core Test Wrapper Optimization for 3D ICs with TSVs,
Brandon Noia, Krishnendu Chakrabarty – Duke University, US - Application of Substrate Noise Simulation Methodology to 3D Stacking,
S. Bronckers, Geert Van der Plas, Pol Marchal – IMEC, BE; Y. Rolain – Vrije Universiteit Brussel, BE - Impact of Thinning on 65nm Device Performance,
Dan Perry, Urmi Ray, Sam Gu, Mark Nakamoto, Wing Sy – Qualcomm, US; Kevin Wang – UC Berkeley, US; Wouter Ruythooren, Bart Swinnen, Yu Yang – IMEC, BE; Jurgen Burggraf, David Matheis-Weiss – EVGroup, AU; C.J. Berry, KiWook Lee, Amkor, US - Bandwidth Optimization for Through Silicon Via Bundles in 3D ICs,
Awet Yemane Weldezion, Li-Rong Zheng, Hannu Tenhunen – KTH, SE; Roshan Weerasekera, Dinesh Pamanuwa – Lancaster University, UK - Water-Level Based Manufacturing Technologies for Realization of TSV and 3D-Based Applications,
Stefan Pargfrieder, Daniel Burgstaller, Otto Bobenstetter, Bioh Kim - EV Group, AU - SOC Test Architecture and Method for 3D-IC,
Chih-Yen Lo, Yu-Tsao Hsing, Li-Ming Deng, Cheng-Wen Wu - National Tsing Hua University, TW - Vertical Links for 3D Network-on-Chip,
Igor Loi, Federico Angiolini, Luca Benini - Universita di Bologna, IT
