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Wednesday, 18 February, 2004
Organisers: Enrico Macii, Politecnico di Torino, Italy
Wolfgang
Nebel, OFFIS, Oldenburg, Germany
Giovanni
De Micheli, Stanford U, USA
Power consumption is a key limitation in many high-speed and
high-data-rate electronic systems today, ranging from mobile
telecom to portable and desktop computing systems, especially
when moving to nanometer technologies where leakage power starts
to dominate. Power is also a showstopper for many emerging applications
like ambient intelligent and sensor networks, some of which
are powered autonomously. Consequently, new design techniques
and design methodologies are needed to control and limit this
power consumption, and not surprisingly this area was the topic
with the largest number of paper submissions in DATE 04
This Special Day therefore focuses on the power problem and
its implications on design techniques and methodologies. It
addresses the difficulties ahead and advanced strategies and
principles for achieving solutions. Major challenges for the
successful design of future highly integrated systems in nanometer
technologies are covered. This Special Day features a full track
of low-power sessions, including one Lunch Keynote speech, two
Special Sessions (one of which consists of an Embedded Tutorial)
and two focused technical sessions.
The Lunch Keynote Speech will be given by Mike Thompson, Operations
Director at STMicroelectronics CR&D, located in Crolles,
France, where he is actively involved in the new collaboration
between STM, Philips, Motorola and TSMC and he has the double
responsibility of managing the 200mm wafer fab and contributing
to the start-up of Crolles 2, the new 300mm state-of-the-art
facility, specialising in high performance technologies for
system-on-chip. The presentation will focus on how different
options in the new technologies can be exploited to provide
very low power consumption in complex SoCs.
The first Special Session addresses issues related to extremely
low-power logic. Three very innovative and promising techniques
will be introduced. The first one concerns ultra low voltage
logic below 0.5 Volt, while the second concerns the design of
ultra low-power, on-chip optical interconnect networks. Finally,
the third contributions will be on power consumption issues
in nanodevices. The second Special Session will be an Embedded
Tutorial covering the design challenges of DSP processor architectures
by looking at previous, current and next generation applications.
LUNCH-TIME KEYNOTE
| Process Technology for
Low-Power Design |
Room Ambroisie 1 and 2,
Level A |
| 1400–1430 |
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| Organisor: |
Mike Thompson,
STMicroelectronics, Operations Director,
CR&D, Crolles, France |
| Thanks to the continued
progress in CMOS technology and manufacturing science,
it is now possible to provide multiple process options
that allow enhancement of particular aspects of the
baseline CMOS, permitting designers to address specific
product and application requirements. These requirements
could be ultra low-noise RF performance, extremely
high-speed digital performance, refined analogue precision,
energy management (high voltage and current capabilities),
very low bit-error rate memories and low power consumption.
After a brief survey of the modular technology approaches
allowing these extra functionalities to be supported,
the talk will concentrate on different options in
the technology and how they can be exploited to provide
very low power consumption in complex SoCs. Finally,
the talk will discuss the interactions that need to
occur between designers, technologists and the wafer
fab in order to provide easy prototyping access to
the technology with first time silicon success and
rapid ramp-up to high yield. |
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SPECIAL TOPIC SESSIONS
| Power Aware Design and
Synthesis |
Room Ambroisie 1 and 2,
Level A |
| 0830–1030 |
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| Moderators: |
R Zafalon, STMicroelectronics,
IT
K Roy, Purdue U, US |
| This session addresses
various issues related to power aware digital designs,
ranging from transistor level leakage minimisation
to advanced clock gating, dynamic VDD scaling, survey
on bus encoding and processor's memory hierarchy exploitation.
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| 0830 |
SIMULTANEOUS
STATE, VT AND TOX ASSIGNMENT FOR TOTAL STANDBY POWER
MINIMIZATION
D Lee, H Deogun, D Blaauw and D Sylvester, Michigan
U, US |
| 0900 |
A SCALABLE
ODC-BASED ALGORITHM FOR RTL INSERTION OF GATED CLOCKS
P Babighian and E Macii, Politecnico di Torino,
IT
L Benini, Bologna U, IT |
| 1000 |
WHY TRANSITION
CODING FOR POWER MINIMIZATION OF ON-CHIP BUSES DOES
NOT WORK
C Kretzschmar and D Mueller, TU Chemnitz, DE
A Nieuwland, Philips Research, NL |
| 1015 |
OVERHEAD-CONSCIOUS
VOLTAGE SELECTION FOR DYNAMIC AND LEAKAGE ENERGY REDUCTION
FOR TIME-CONSTRAINED APPLICATIONS
A Andrei, M Schmitz, P Eles and Z Peng, Linkoping
U, SE
B Al-Hashimi, Southampton U, UK |
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| HOT TOPIC – Extremely
Low Power LogicPower Aware Design and Synthesis |
Room Ambroisie 1 and 2,
Level A |
| 1130–1300 |
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Organiser/
Moderator: |
C Piguet, CSEM, CH |
| For extremely low-power
logic, three very new and promising techniques will
be described. The first is ultra low voltage logic
below 0.5 to 0.4 Volt. The second will focus on the
interconnect issues in large chips by discussing on-chip
optical interconnect networks. Finally, nano-devices
will be presented, as a possibility to compute with
nearly zero power, and compared to future 10 nanometer
transistors. |
| 1130 |
ULTRA LOW VOLTAGE
LOGIC
C Heer, Infineon Technologies, DE
U Schlichtmann, TU Munich, DE |
| 1200 |
ON-CHIP OPTICAL
INTERCONNECT FOR LOW-POWER
I O’Connor, Ecole Centrale de Lyon, FR |
| 1230 |
NANO DEVICES
FOR LOW POWER
J Gautier, LETI, Grenoble, FR |
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| Power-Aware Networks and
Interfaces |
Room Ambroisie 1 and 2,
Level A |
| 1430–1600 |
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| Moderators: |
M Pedram, Southern
California U, US
A Amara, ISEP, FR |
| The focus of this session
is on energy efficiency in networks and chips. Presented
techniques include 1) data filtering and remote data
swapping in wireless networks, and 2) interface synthesis
and asynchronous design for integrated circuits. |
| 1430 |
TUNING IN-SENSOR
DATA FILTERING TO REDUCE ENERGY CONSUMPTION IN WIRELESS
SENSOR NETWORKS
I Kadayif, Canakkale Onsekiz Mart U, TK
M Kandemir, Penn State U,US |
| 1500 |
POWER-AWARE
NETWORK SWAPPING FOR WIRELESS PALMTOP PCS
A Acquaviva, E Lattanzi and A Bogliolo, Urbino U,
IT |
| 1530 |
POWER AWARE
INTERFACE SYNTHESIS FOR BUS-BASED SOC DESIGN
N D Liveris and P Banerjee, Northwestern U, Evanston,
US |
| 1545 |
ASYNCHRONOUS
DESIGN BY CONVERSION: CONVERTING SYNCHRONOUS CIRCUITS
INTO ASYNCHRONOUS ONES
A Branover, R Kol and R Ginosar, Technion-Israel Inst.
of Tech., IL |
|
| EMBEDDED TUTORIAL –
Architectures and Design Techniques for Energy Efficient
Embedded DSP and Multimedia Processing |
Room Ambroisie 1 and 2,
Level A |
| 1630-1800 |
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| Organiser: |
E Macii, Politecnico
di Torino, IT |
| Moderator: |
N Chang, Seoul National
U, KR |
| Speakers: |
I Verbauwhede,
UCLA, US
C Piguet, CSEM, CH
P Schaumont, UCLA, US
B Kienhuis, Leiden U, NL |
| A good balance between
energy efficiency and programmability can be obtained
in modern embedded systems by resorting to programmable
domain-specific processors. A well known example of
these are programmable digital signal processors (DSPs).
DSPs are developed with wireless communications in
mind (mostly driven by cellular standards). In a first
generation this meant that DSPs were adapted to execute
many types of filters (e.g. FIR, IRR), later communication
algorithms such as Viterbi decoding and more recently
Turbo decoders and speech coding and decoding algorithms
are added. This tutorial will cover in details the
design challenges of DSP processor architectures by
looking at previous, current and next generation applications.
The demands of the application are illustrated by
architectural approaches of different DSP and design
methods to support the design of these heterogeneous
architectures will be described. |
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