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| Session: |
PCB Symposium: Signal Integrity
in Multi-Gigabit Designs |
Downloadable |
| Thu |
0830-1300
Room: Dickens 1 & 2, Level D |
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PCB Symposium:
Signal Integrity in Multi-Gigabit Designs [8F
9F] |
[PDF 600 KB] |
| Org/Mod: |
carsten_elgert@mentor.com |
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This year’s PCB Symposium which
forms part of the free Exhibition Programme is themed Signal
Integrity in Multi-Gigabit Designs. While Signal-Integrity
effects occur today even on the simplest boards, the PCBengineer
faces a design discontinuity with completely new challenges
when working on boards containing 3rd-generation serial
I/O technology components. Prof. Thueringer from FH Giessen
will present a keynote, covering fundamentals of signal
integrity effects. Following are technical presentations
by users and EDA vendors focusing on their experiences in
designing systems-on-board and providing solutions for key
challenges in this area. The target audience are the PCB-
and System-design engineers who are involved in developing
leading-edge products. Attendance at this session is free
of charge and does not require pre-registration.
Please contact carsten_elgert@mentor.com no later than
Jan 09, 2004 for details. |
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| Thu |
0830 Room:
Dickens 1 and 2, Level D |
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Keynote: ‘Todays
Challenges in High Speed Design’ [8F] |
[PDF 7.3 MB] |
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| Spks/Pans: |
Prof. Thueringer, FH Giessen |
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| Thu |
0930 Room:
Room Dickens 1 and 2, Level D |
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User Paper1: Ibis
Modelling, benefits and limitations [8F] |
[PDF 400 KB] |
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| Spks/Pans: |
Eckhard Lenski, Siemens
AG |
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| Thu |
1000 Room:
Dickens 1 and 2, Level D |
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Vendor paper 1
– Analysis Driven Routing Controlled by an Analogue Digital
Mixed Signal Simulator: [8F] |
[PDF 4 MB] |
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| Spks/Pans: |
Stephane Rousseau, Mentor
Graphics |
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| 1030 |
SESSION BREAK |
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| Thu |
1130 Room:
Dickens 1 and 2, Level D |
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Vendor Paper 2:
Behavioural Modelling for I/Os and Interconnect Structures
for Applications in the GHz range: [9F] |
[PDF 4.7 MB] |
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| Spks/Pans: |
Heiko Dudek, Cadence |
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| Thu |
1200 Room:
Dickens 1 and 2, Level D |
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Vendor Paper 3:
How to profit from losses: Beginners guide to lossy and
lossless transmission lines: [9F] |
[PDF 3 B] |
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| Spks/Pans: |
Ralf Brüning, Zuken |
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| Thu |
1230 Room:
Dickens 1 and 2, Level D |
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User Paper 2:
An efficient design process flow for Complex PCB design: [9F] |
[PDF 1.5 MB] |
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| Spks/Pans: |
Jean-Claude Simon, Alcatel |
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| 1300 |
LUNCH |
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