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Tuesday, 17 February, 2004
Organiser: Joan Figueras, UPC, ES
EYervant Zorian, Virage Logic,
US
DATE 04 will host a full day programme of executives’
presentations, representing a range of leading semiconductor
manufacturers, EDA vendors, IP providers and test technology
suppliers.
This one day programme will be composed of four sessions where
executives will present their technical/business vision in the
domains of design, automation and test, plus the technical keynote.
The four sessions will be comprised of one plenary executive
lunch panel featuring the CEOs of the three largest EDA companies,
and three 1.5 hour sessions featuring 5-6 executives each and
running in parallel to the technical conference tracks. All
four executive sessions will first provide each executive with
a time-slot to present his/her vision, followed by a question
and answer period to provide interaction with the attendees.
This new track should offer prospective attendees valuable information
about the vision and roadmaps of their corresponding companies
from a business and technology point-of-view.
Fees for the Executive Track are the same as for the regular
DATE Conference technical presentations. Registration includes
coffee, lunch and conference proceedings. Pre-registration online
is encouraged and there is an early bird discount for registrations
made before January 25th, 2004. ENTRY TO THE KEYNOTE and LUNCH
TIME PANEL IS FREE.
DATE Keynote
0930 – 1015
Amphitheatre Goethe
OPPORTUNITIES AND CHALLENGES IN BUIDING SILICON PRODUCTS
IN 65nm AND BEYOND
Gregory S Spirakis
Vice-President, Mobile Platforms Group and Director of Design
Technology
Intel, US
The demand for cheaper, faster and more integrated semiconductor
products is expected to drive the scaling of Silicon Technology,
enabling continuance of Moore’s law at least for another
decade. However, technology scaling presents several manufacturing
and design technology challenges that must be overcome to build
semiconductor products in a cost effective manner. While some
of the existing challenges that we face today such as power,
process variations are expected to become worse at smaller geometries
requiring innovations, new problems may arise in integrating
heterogeneous technologies such as RF, MEMS on the same die/package.
A myriad of design technology challenges starting from functional
validation to timing validation and design for test to manufacturability
must be addressed to successfully build products.
Executive Track
Room Ambroisie 1 and 2, Level A
| 1G Managing Design Complexity
in 90nm Technology |
Room Ambroisie 1 and 2,
Level A |
| 1100-1230 |
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| Moderators: |
N Mokhoff, EE Times,
US |
| Executives: |
R Blake, VP
Product Planning, Altera, US
E H Frank, VP Research & Development, Broadcom,
US
A Kablanian, President & CEO, Virage Logic, US
C King, President & CEO, AMI Semiconductor, US
K den Otter, President, TSMC Europe, NL
C Rowen, President & CEO, Tensilica, US |
| Semiconductor process
technology has been advancing at a tremendous pace
over the past decades. The 90nm technology will allow
us to use hundreds of millions of transistors in a
single design. How are we going to manage the design
complexity? This session will allow a number of executives
to address these challenges and the design methodologies
needed to reach the necessary productivity. |
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| 1K PANEL – The Future
of EDA: CEO Perspective |
Room Ambroisie 1 and 2,
Level A |
| 1345-1430 |
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| Moderators: |
G Smith, Dataquest,
US |
| Executives: |
R Bingham,
President & CEO, Cadence, US
A de Geus, President & CEO, Synopsys, US
W Rhines, President & CEO, Mentor Graphics, US |
| The executive lunch
panel will provide the chance for DATE attendees to
hear from the executives of the three largest EDA
companies about their business perspective and corresponding
R&D efforts, with some emphasis on the plans for
”R” in the R&D. |
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| 2G Determining the Value
of Test |
Room Ambroisie 1 and 2,
Level A |
| 1430-1600 |
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| Moderators: |
R Wilson, EE Times,
US |
| Executives: |
Jim Healy,
LogicVision, US
N Konidaris, President & CEO, Advantest America,
US
P Magarshack, Group VP, Central R&D, STMicroelectronics,
FR
C Vandenberg, President & CEO, HPL, US
R Vashista, VP Technology Marketing, LSI Logic, US |
| Test has mainly been
used to screen defective units to ship the remaining
fault-free ones, thus considering test a technology
with a negative impact on the bottom line. With the
very deep micron technologies, the impact of test
is widening from a screening technology to one that
helps debugging the first silicon, to a basis for
repairing chips during manufacturing and in the field,
to an infrastructure for diagnosis and fault tolerance.
A number of executives in this session will discuss
the value of test. |
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| 3G Advanced Solutions
for SoC Design |
Room Ambroisie 1 and 2,
Level A |
| 1630-1800 |
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| Moderators: |
P Aycinena, EDA Weekly,
US |
| Executives: |
J Benkoski,
President & CEO, Monterey Design Systems, US
M Muller, CTO, ARM, UK
A Naumann, President & CEO, CoWare, US
T Reeves, VP & GM, IBM Microelectronics, ASIC
Division, US
S Wang, VP Strategy & Bus Dev, Axis Systems, US |
| System level design
concerns are now dominating the definition of new
platforms for future electronic systems. EDA tools
need to address on the one hand the sub-nanometer
physical design and manufacturability challenges and
on the other move from the register-transfer-level
to a higher level of abstraction, the electronic system
level. The executives in this session will address
the advanced solutions to achieve the above. |
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