D7 Formal Methods and Verification

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Chair: Wolfgang Kunz
TU Kaiserslautern, DE
kunz at eit [dot] uni-kl [dot] de

Co-Chair: Gianpiero Cabodi
Politecnico di Torino, IT
gianpiero [dot] cabodi at polito [dot] it

Formal verification and specification techniques (including  equivalence checking, model checking, symbolic simulation,  theorem-proving, abstraction and refinement techniques, and real time  verification); technologies supporting formal verification (including SMT, SAT, BDD, ATPG, and related work); semi-formal verification techniques; applications and case studies; formal verification of IPs,  SoCs, cores and real-time/embedded systems; verification in practice,  namely the integration of verification into the design flow.