D10 Architectural and High-Level Synthesis

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Chair: Paolo Ienne
EPFL, CH
paolo [dot] ienne at epfl [dot] ch

Co-Chair: Philippe Coussy
University of Bretagne-Sud, FR
philippe [dot] coussy at univ-ubs [dot] fr

Synthesis of hardware systems from high-level descriptions; hardware-centric system-level synthesis, analysis, and optimization; high-level language hardware description, parsing and compilation; scheduling, allocation, and binding of operations, variables, and transfers;  automatic design and optimization of datapaths, dedicated memory and communication structures, and controllers; performance, cost, and power driven architectural-level optimisations; application-specific processor generation, automatic processor customization, and accelerator synthesis.