DATE 2008 TABLE OF CONTENTS ...

Cover Page
DATE Executive Committee
DATE Sponsors Committee
Technical Program Chairs
Technical Program Committee
Reviewers
Foreword
Best Paper Awards
Tutorials
PH.D. Forum
Call for Papers: DATE 2009

Keynote Addresses

Designing Micro/Nano Systems for a Safer and Healthier Tomorrow [p. 1]

G. De Micheli

Perspective on Embedded Systems: Challenges, Solutions and Research Priorities [p. 2]

D. Vernay

1.2: Transaction-Level Modelling (TLM)

Cycle-approximate Retargetable Performance Estimation at the Transaction Level [p. 3]

Y. Hwang, S. Abdi and D. Gajski

A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip [p. 9]

J. Cornet, F. Maraninchi and L. Maillet-Contoz

Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation [p. 15]

N. Bombieri, N. Deganello and F. Fummi

1.3: Invited Industrial Session - Industrial System Designs in Transportation and Information Technologies

Tailored Solutions for Safety-Installations in the Loetschberg Tunnel - A Project with Importance for the Trans-European Rail Traffic [p. 21]

W. Fuβ

On the Verification of High-Order Constraint Compliance in IC Design [p. 26]

J. Freuer, G. Jerke, J. Gerlach and W. Nebel

Industrial IP Integration Flows Based on IP-XACT^TM Standards [p. 32]

W. Kruijtzer, P. van der Wolf, E. de Kock, J. Stuyt, W. Ecker, A. Mayer, S. Hustin, C. Amerijckx, S. de Paoli and E. Vaumorin

1.4: Application of Reconfigurable and Adaptive Systems

A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment [p. 38]

T. Vogt and N. Wehn

Using Reconfigurable Logic to Optimise GPU Memory Accesses [p. 44]

B. Cope, P. Y. K. Cheung and W. Luk

Cost - And Power Optimized FPGA Based System Integration: Methodologies and Integration of a Low-Power Capacity- Based Measurement Application on Xilinx FPGAs [p. 50]

K. Paulsson, M. Hübner and J. Becker

Design Flow for Embedded FPGAs Based on a Flexible Architecture Template [p. 56]

B. Neumann, T. Von Sydow, H. Blume and T. G. Noll

1.5: Advances in BIST Techniques for Mixed-Signal Devices

Optimal High-Resolution Spectral Analyzer [p. 62]

A. Tchegho, H. Mattes and S. Sattler

A General Method to Evaluate RF BIST Techniques Based on Non-Parametric Density Estimation [p. 68]

H.-G. Stratigopoulos, J. Tongbong and S. Mir

Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters [p. 74]

A. Zjajo and J. Pineda De Gyvez

Practical Implementation of a Network Analyzer for Analog BIST Applications [p. 80]

M.J. Barragán, D. Vázquez and A. Rueda

1.6: HOT TOPIC - Quantitative Evaluation in Embedded Systems Design

Quantitative Evaluation in Embedded System Design: Trends in Modeling and Analysis Techniques [p. 86]

J.-P. Katoen

Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures [p. 88]

N. Coste, H. Garavel, H. Hermanns, R. Hersemeule, Y. Thonnart and M. Zidouni

Quantitative Evaluation in Embedded System Design: Predicting Battery Lifetime in Mobile Devices [p. 90]

L. Cloth and B.R. Haverkort

1.7: System-Level Power Management and Energy Harvesting

A Framework of Stochastic Power Management Using Hidden Markov Model [p. 92]

Y. Tan and Q. Qiu

Harvesting Wasted Heat in a Microprocessor Using Thermo-Electric Generators: Modeling, Analysis And Measurement [p. 98]

Y. Zhou, S. Paul and S. Bhunia

An Efficient Solar Energy Harvester for Wireless Sensor Nodes [p. 104]

D. Brunelli, L. Benini, C. Moser and L. Thiele

Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization [p. 110]

S. Murali, A. Mutapcic, D. Atienza, R. Gupta, S. Boyd, L. Benini and G. De Micheli

2.2: Heterogeneous System Modelling, Analysis and Implementation

Parametric Throughput Analysis of Synchronous Data Flow Graphs [p. 116]

A. H. Ghamarian, M.C.W. Geilen, T. Basten and S. Stuijk

Introducing Preemptive Scheduling in Abstract RTOS Models Using Result Oriented Modeling [p. 122]

G. Schirner and R. Dömer

SystemC-Based Modeling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder [p. 128]

K. Grüttner, F. Oppenheimer, W. Nebel, F. Colas-Bigey and A.-M. Fouilliart

Modeling and Refining Heterogeneous Systems with SystemC-AMS: Application to WSN [p. 134]

M. Vasilevski, F. Pecheux, N. Beilleau, H. Aboshady and K. Einwich

2.3: New Directions in Analogue Circuit Modelling

Sizing Rules for Bipolar Analog Circuit Design [p. 140]

T. Massier, H. Graeb and U. Schlichtmann

Efficient Circuit-Level Modeling of Ballistic CNT Using Piecewise Non-Linear Approximation of Mobile Charge Density [p. 146]

T. J. Kazmierski, D. Zhou and B. M. Al-Hashimi

A New Approach for Combining Yield and Performance in Behavioral Models for Analogue Integrated Circuits [p. 152]

S. Ali, R. Wilcock, P. Wilson and A. Brown

2.4: Automotive System Design and Verification

Symbolic Reliability Analysis and Optimization of ECU Networks [p. 158]

M. Glaβ, M. Lukasiewycz, F. Reimann, C. Haubelt and J. Teich

Verification of Temporal Properties in Automotive Embedded Software [p. 164]

D. Lettnin, P.K. Nalla, J. Ruf, T. Kropf, W. Rosenstiel, T. Kirsten, V. Schönknecht and S. Reitemeyer

A Novel Approach for EMI Design of Power Electronics [p. 170]

B. Stube, B. Schroeder, E. Hoene and A. Lissner

Hardware/Software Architecture of an Algorithm for Vision-Based Real-Time Vehicle Detection in Dark Environments [p. 176]

N. Alt, C. Claus and W. Stechele

2.5: Advances in SoC Test

Analysis of the Test Data Volume Reduction Benefit of Modular SOC Testing [p. 182]

O. Sinanoglu and E. J. Marinissen

Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns [p. 188]

A. Larsson, E. Larsson, K. Chakrabarty, P. Eles and Z. Peng

A Novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers [p. 194]

P. Bernardi and M. Sonza Reorda

2.6: Performance Analysis and Exploration of MPSoC Architectures

Performance Analysis of SoC Architectures Based on Latency-Rate Servers [p. 200]

J. P. Vink, K. Van Berkel and P. Van Der Wolf

Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs [p. 206]

S. Pandey and R. Drechsler

Run-Time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSoC) [p. 212]

P.K.F. Hölzenspies, J.L. Hurink, J. Kuper and G.J.M. Smit

Architecture Exploration of NAND Flash-Based Multimedia Card [p. 218]

S. Kim, C. Park and S. Ha

2.7: Advanced Power Management Techniques

Resilient Dynamic Power Management under Uncertainty [p. 224]

H. Jung and M. Pedram

Robust and Low Complexity Rate Control for Solar Powered Sensors [p. 230]

C. Moser, L. Thiele, D. Brunelli and L. Benini

Energy Aware Dynamic Voltage and Frequency Selection for Real-Time Systems with Energy Harvesting [p. 236]

S. Liu, Q. Qiu and Q. Wu

Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution [p. 242]

S. Hong, S. Yoo, B. Bin, K.-M. Choi, S.-K. Eo and T. Kim

IP1 Interactive Presentations

Built-In Clock Skew System for On-Line Debug and Repair [p. 248]

A. Chattopadhyay and Z. Zilic

Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects [p. 252]

R. Rimolo-Donadio, C. Schuster, X. Gu, Y.H. Kwark and M.B. Ritter

On Automated Trigger Event Generation in Post-Silicon Validation [p. 256]

H.F. Ko and N. Nicolici

Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems [p. 260]

K.W. Batcher and R.A. Walker

Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking [p. 264]

Y. Qu, J.-P. Soininen and J. Nurmi

Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-Based Integration [p. 268]

M. Dong and L. Zhong

Merged Computation for Whirlpool Hashing [p. 272]

R. Chaves, G. Kuzmanov, L. Sousa and S. Vassiliadis

Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor [p. 276]

T. Meyerowitz, A. Sangiovanni-Vincentelli, M. Sauermann and D. Langen

Safe Automatic Flight Back and Landing of Aircraft. Flight Reconfiguration Function (FRF) [p. 280]

J.A. Herrería García

PWM-Based Test Stimuli Generation for BIST of High Resolution Sigma-Delta ADCS [p. 284]

D. De Venuto and L. Reyneri

3.2: System Synthesis

Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs [p. 288]

T. Chantem, R.P. Dick and X.S. Hu

A Formal Approach to the Protocol Converter Problem [p. 294]

K. Avnit, V. D'Silva, A. Sowmya, S. Ramesh and S. Parameswaran

Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip [p. 300]

A. Moonen, M. Bekooij, R. van den Berg and J. van Meerbergen

Synthesizing Synchronous Elastic Flow Networks [p. 306]

G. Hoover and F. Brewer

3.3: Analogue Simulation, Synthesis and Verification

Periodic Steady-State Analysis Augmented with Design Equality Constraints [p. 312]

I. Vytyaz, P.K. Hanumolu, U.-K. Moon and K. Mayaram

Analysis of Oscillator Injection Locking by Harmonic Balance Method [p. 318]

M.M. Gourary, S.G. Rusakov, S.L. Ulyanov, M.M. Zharov, B.J. Mulvaney and K.K. Gullapalli

Model Checking of Analog Systems Using an Analog Specification Language [p. 324]

S. Steinhorst and L. Hedrich

3.4: Aerospace Designs and MEMs Systems

Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components [p. 330]

G. Gailliard, H. Balp, M. Sarlotte and F. Verdier

On the Design of Tunable Fault Tolerant Circuits on SRAM-Based FPGAs for Safety Critical Applications [p. 336]

L. Sterpone, M. Aguirre, J. Tombs and H. Guzmán-Miranda

Hot Wire Anemometric MEMs Sensor for Water Flow Monitoring [p. 342]

M. Melani, L. Bertini, M. De Marinis, P. Lange, F. D'Ascoli and L. Fanucci

3.5: Fault Tolerant Techniques

Guiding Circuit Level Fault-Tolerance Design with Statistical Methods [p. 348]

D.C. Ness and D.J. Lilja

A Delay-Efficient Radiation-Hard Digital Design Approach Using CWSP Elements [p. 354]

C. Nagpal, R. Garg and S.P. Khatri

Towards Fault Tolerant Parallel Prefix Adders in Nanoelectronic Systems [p. 360]

W. Rao and A. Orailoglu

A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking [p. 366]

S. Ghosh, P. Ndai and K. Roy

3.6: EMBEDDED TUTORIAL - Software for Wireless Networked Embedded Systems

Software for Wireless Networked Embedded Systems [p. 372]

Presenters: A. Dunkels, K. Langendoen, J. Beutel

3.7: Power Optimisation by Supply and Ground Voltage Control

Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction [p. 373]

L. Leinweber and S. Bhunia

A Scalable Algorithmic Framework FOR Row-Based Power-Gating [p. 379]

A. Sathanur, A. Pullini, L. Benini, A. Macii, E. Macii and M. Poncino

Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay-Budgeting [p. 385]

E. Pakbaznia and M. Pedram

4.1: Physical Architectures (Automotive Systems Day)

Physical Architectures of Automotive Systems [p. 391]

T. Forest, A. Ferrari, G. Audisio, M. Sabatini, A. Sangiovanni-Vincentelli and M. Di Natale

4.2: High-Level Models for Validation

A Mutation Model for the SystemC TLM 2.0 Communication Interfaces [p. 396]

N. Bombieri, F. Fummi and G. Pravadelli

Efficient Design Validation Based on Cultural Algorithms [p. 402]

W. Wu and M.S. Hsiao

Algorithms for Maximum Satisfiability Using Unsatisfiable Cores [p. 408]

J. Marques-Silva and J. Planes

In-Band Cross-Trigger Event Transmission for Transaction-Based Debug [p. 414]

S. Tang and Q. Xu

4.3: Power Grid and Interconnect Modelling

Efficient Representation and Analysis of Power Grids [p. 420]

J.M.S. Silva, J.R. Phillips and L.M. Silveira

High-Frequency Mutual Impedance Extraction of VLSI Interconnects in the Presence of a Multi-Layer Conducting Substrate [p. 426]

N. Srivastava, R. Suaya and K. Banerjee

ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis [p. 432]

D. Li, S.X.-D. Tan and B. McGaughy

Bandwidth-Centric Optimization for Area-Constrained Links with Crosstalk Avoidance Methods [p. 438]

B. Halak and A. Yakovlev

4.4: Algorithms and Architectures Optimisation for Baseband Processing

Optimizating Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures [p. 444]

M. Li, B. Bougard, D. Novo, L. Van Der Perre and F. Catthoor

Vectorization of Reed Solomon Decoding and Mapping on the EVP [p. 450]

A. Kumar and K. Van Berkel

A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder [p. 456]

M. May, M. Alles and N. Wehn

4.5: DFX: Support for Test, Manufacturing, and Diagnosis

Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction [p. 462]

A. Chandra, F. Ng and R. Kapur

Scan Chain Organization for Embedded Diagnosis [p. 468]

M. Elm and H.-J. Wunderlich

State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores [p. 474]

V. Tenentes, X. Kavousianos and E. Kalligeros

Automated Testability Enhancements for Logic Brick Libraries [p. 480]

J.G. Brown, B. Taylor, R.D.S. Blanton and L. Pileggi

4.6: Model-Based Design for Embedded Systems

A Game-Theoretic Approach to Real-Time System Testing [p. 486]

A. David, K.G. Larsen, S. Li and B. Nielsen

Modeling Event Stream Hierarchies with Hierarchical Event Models [p. 492]

J. Rox and R. Ernst

Semantics for Model-Based Validation of Continuous/Discrete Systems [p. 498]

L. Gheorghe, F. Bouchhima, G. Nicolescu and H. Boucheneb

Using UML as Front-End for Heterogeneous Software Code Generation Strategies [p. 504]

L.B. Brisolara, M.F.S. Oliveira, R. Redin, L.C. Lamb, L. Carro and F. Wagner

4.7: PANEL SESSION - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm

PANEL - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm [p. 510]

Panelists: R. Aitken, R. Lauwereins, J. Tracy Weed, V. Kiefer and J. Hartmann [p

IP2 Interactive Presentations

Fault Clustering in Deep-Submicron CMOS Processes [p. 511]

J. Schat

Energy Efficient and High Speed On-Chip Ternary Bus [p. 515]

C. Duan and S.P. Khatri

Task Scheduling with Configuration Prefetching and Anti-Fragmentation Techniques on Dynamically Reconfigurable Systems [p. 519]

F. Redaelli, M.D. Santambrogio and D. Sciuto

Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches [p. 523]

A. Pradhan and R. Vemuri

Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression [p. 527]

B. Liu

A Methodology for Improving Software Design Lifecycle in Embedded Control Systems [p. 533]

M.E.M. Ben Gaid, R. Kocik, Y. Sorel and R. Hamouche

Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network [p. 537]

W. Zhang, Y. Zhu, W. Yu, L. Zhang, R. Shi, H. Peng, Z. Zhu, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito and C.-K. Cheng

A System Architecture for Reconfigurable Trusted Platforms [p. 541]

B. Glas, A. Klimm, O. Sander, K. Müller-Glaser and J. Becker

Automatic Generation of Complex Properties for Hardware Designs [p. 545]

F. Rogin, T. Klotz, G. Fey, R. Drechsler and S. Rülke

5.1.1: Software Components for Reliable Automotive Systems (Automotive Systems Day)

Software Components for Reliable Automotive Systems [p. 549]

H. Heinecke, W. Damm, B. Josko, A. Metzner, H. Kopetz, A. Sangiovanni-Vincentelli and M. Di Natale

5.1.2: LUNCH-TIME KEYNOTE (Automotive Systems Day)

Model-Based-Design is Nice, But... [p. 555]

H. Hanselmann

5.2: Timing-Based Validation

A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real- Time Systems [p. 556]

S. Samii, S. Rafiliu, P. Eles and Z. Peng

Signal Probability Based Statistical Timing Analysis [p. 562]

B. Liu

A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect [p. 568]

B. Amelifard, S. Hatami, H. Fatemi and M. Pedram

Current Source Based Standard Cell Model for Accurate Signal Integrity and Timing Analysis [p. 574]

A. Goel and S. Vrudhula

5.3: Variation-Aware Modelling of Gates and Interconnects

An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation [p. 580]

W. Zhang, W. Yu, Z. Wang, Z. Yu, R. Jiang and J. Xiong

SPARE - A Scalable Algorithm for Passive, Structure Preserving, Parameter-Aware Model Order Reduction [p. 586]

J. Fernández Villena and L.M. Silveira

Transistor-Specific Delay Modeling for SSTA [p. 592]

B. Cline, K. Chopra, D. Blaauw, A. Torres and S. Sundareswaran

5.4: Signal Processing on Massive Parallel Architectures

Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications [p. 598]

M. Li, D. Novo, B. Bougard, L. Van Der Perre and F. Catthoor

A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms [p. 604]

R. Koenig, T. Stripf and J. Becker

Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA [p. 610]

P. Bonnot, F. Lemonnier, G. Edelin, G. Gaillat, O. Ruch and P. Gauget

5.5: Statistical, Physical Defect Based Testing

On Modeling and Testing of Lithography Related Open Faults In Nano-CMOS Circuits [p. 616]

A. Sreedhar, A. Sanyal and S. Kundu

Optimal Margin Computation for At-Speed Test [p. 622]

J. Xiong, V. Zolotov, C. Visweswariah and P.A. Habitz

Resistive Bridging Fault Simulation of Industrial Circuits [p. 628]

P. Engelke, I. Polian, J. Schloeffe and B. Becker

Physically-Aware N-Detect Test Pattern Selection [p. 634]

Y.-T. Lin, O. Poku, N.K. Bhatti and R.D.S. Blanton

5.6: Tuning System Parameters for QoS Constrained Multimedia Appications

Computation of Buffer Capacities for Throughput Constrained and Data Dependent Inter- Task Communication [p. 640]

M.H. Wiggers, M.J.G. Bekooij and G.J.M. Smit

Constraint Refinement for Online Verifiable Cross-Layer System Adaptation [p. 646]

M. Kim, M.-O. Stehr, C. Talcott, N. Dutt and N. Venkatasubramanian

Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-Time Applications with Non-Deterministic Workload [p. 652]

P. Malani, P. Mukre, Q. Qiu and Q. Wu

5.7: EMBEDDED TUTORIAL - ARTEMIS and ENIAC Joint Undertakings: A New Approach to Conduct Research in Europe

ARTEMIS and ENIAC Joint Undertakings: A New Approach to Conduct Research in Europe [p 658]

Presenters: K. Glinos, D. Beenaert, L. Gide

6.1: Methods, Tools and Standards for the Analysis and Evaluation of Modern Automotive Architectures (Automotive Systems Day)

Methods, Tools and Standards for the Analysis and Evaluation of Modern Automotive Architectures [p. 659]

E. Frank, R. Wilhelm, R. Ernst, A. Sangiovanni-Vincentelli and M.Di Natale

6.2: Simulation-Based Validation

Random Stimulus Generation Using Entropy and XOR Constraints [p. 664]

S.M. Plaza, I.L. Markov and V. Bertacco

MCjammer: Adaptive Verification for Multi-Core Designs [p. 670]

I. Wagner and V. Bertacco

Efficient Implementation of Native Software Simulation for MPSoC [p. 676]

P. Gerin, X. Guérin and F. Pétrot

Simulation-Directed Invariant Mining for Software Verification [p. 682]

X. Cheng and M.S. Hsiao

6.3: Robust Mixed-Signal System Design

Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation [p. 688]

M. Momeni, P.B. Bacinschi and M. Glesner

A Novel Technique for Improving Temperature Independency of Ring-ADC [p. 694]

S. Li, H. Chen and F. Zhou

An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs [p. 698]

P.B. Bacinschi, T. Murgan, K. Koch and M. Glesner

Integrated Approach to Energy Harvester Mixed Technology Modeling and Performance Optimization [p. 704]

L. Wang, T.J. Kazmierski, B.M. Al-Hashimi, S.P. Beeby and R.N. Torah

6.4: Architectures for Wireless Communications

A Scalable Low-Power Digital Communication Network Architecture and an Automated Design Path for Controlling the Analog/RF Part of SDR Transceivers [p. 710]

W. Eberle and M. Goffioul

A Coarse-Grained Array Based Baseband Processor for 100mbps+ Software Defined Radio [p. 716]

B. Bougard, B. De Sutter, S. Rabou, D. Novo, O. Allam, S. Dupont and L. Van der Perre

Scenario-Based Fixed-Point Data Format Refinement to Enable Energy-Scalable Software Defined Radios [p. 722]

D. Novo, B. Bougard, A. Lambrechts, L. Van der Perre and F. Catthoor

6.5: HOT TOPIC - Test Challenges for Low Power Devices

Test Strategies for Low Power Devices [p. 728]

C.P. Ravikumar, M. Hirech and X. Wen

6.6: Software Architectures for Embedded Multi-CPU Systems

Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures [p. 734]

F. Mulas, M. Pittau, M. Buttu, S. Carta, A. Acquaviva, L. Benini, D. Atienza and G. De Micheli,

A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs [p. 740]

O. Certner, Z. Li, P. Palatin, O. Temam, F. Arzel and N. Drach

Exact and Approximate Task Assignment Algorithms for Pipelined Software Synthesis [p. 746]

M. Hashemi and S. Ghiasi

6.7: Instruction-Set Optimisations

Run-Time System for an Extensible Embedded Processor with Dynamic Instruction Set [p. 752]

L. Bauer, M. Shafique, S. Kreutz and J. Henkel

Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency [p. 758]

H. Lin and Y. Fei

Instruction Set Extension Exploration in Multiple-Issue Architecture [p. 764]

I.-W. Wu, Z.-Y. Chen, J.-J. Shann and C.-P. Chung

Instruction Re-Encoding Facilitating Dense Embedded Code [p. 770]

T. Bonny and J. Henkel

IP3 Interactive Presentations

Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM Devices [p. 776]

M. Versen, A. Schramm, J. Schnepp and D. Diaconescu

A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs [p. 780]

B. Ristau, T. Limberg and G. Fettweis

Impact of Leakage Current on Data Retention of RF-Powered Devices during Amplitude-Modulation-Based Communication [p. 784]

J. Haid, B. Zimek, T. Leutgeb and T. Kuenemund

Accuracy-Adaptive Simulation of Transaction Level Models [p. 788]

M. Radetzki and R.S. Khaligh

Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor [p. 792]

J. Wang, H. Zeng, K. Huang, G. Zhang and Y. Tang

Wire Sizing Alternative - An Uniform Dual-Rail Routing Architecture [p. 796]

F.-W. Chen and Y.-Y. Liu

Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology [p. 800]

X. Wang and L. Hedrich

A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design [p. 804]

A. Lewicki, J. del Prado Pavon, J. Talayssat, E. Dekneuvel and G. Jacquemod

Re-Examining the Use of Network-on-Chip as Test Access Mechanism [p. 808]

F. Yuan, L. Huang and Q. Xu

7.1: PANEL SESSION - The Future Car: Technology, Methods and Tools (Automotive Systems Day)

PANEL - The Future Car: Technology, Methods and Tools [p. 812]

Panelists: H. Hanselmann, H. Heineke, A. Bouali, H. Kopetz, H. Fennel and T. Weber

7.2: Formal Methods for Hardware and Software Verification

Improving Constant-Coefficient Multiplier Verification by Partial Product Identification [p. 813]

C.-Y. Lai and C.-Y. Huang and K.-Y. Khoo

Improved Visibility in One-to-Many Trace Concretization [p. 819]

K. Nanshi and F. Somenzi

Efficient Symbolic Simulation of Low Level Software [p. 825]

T. Arons, E. Elster, S. Ozer, J. Shalev and E. Singerman

Completeness in SMT-Based BMC for Software Programs [p. 831]

M.K. Ganai and A. Gupta

7.3: Physical Design: From Pins to Transistors

Novel Pin Assignment Algorithms for Components with Very High Pin Counts [p. 837]

T. Meister, J. Lienig and G. Thomke

A Generic Standard Cell Design Methodology for Differential Circuit Styles [p. 843]

S. Badel, E. Güleyüpoglu, O. Inaç, A.P. Martinez, P. Vietti, F.K. Gürkaynak and Y. Leblebici

Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices [p. 849]

A. Chakraborty, X. Shi and D.Z. Pan

Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing [p. 856]

A. Singhee, S. Singhal and R.A. Rutenbar

7.4: Advanced Design Techniques for Sensor and Communication Applications

A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications [p. 862]

A. Morgado, R. del Río and J.M. de la Rosa

Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement [p. 868]

M. Bingesser, T. Loeliger, W. Hinn, J. Hauer, S. Mödl, R. Dorn and M. Völker,

Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment [p. 873]

M. Badaroglu, G. Decabooter, F. Laulanet and O. Charlier

A Programmable and Low-EMI Integrated Half-Bridge Driver IN BCD Technology [p. 879]

F. D'Ascoli, L. Bacciarelli, M. Melani, L. Fanucci, G. Ricotti, E. Pardi, F. Vincis, M Forliti and M. De Marinis

7.5: Design Techniques for Error Mitigation

CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns [p. 885]

Y. Li, S. Makar and S. Mitra

Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology [p. 891]

L. Zhang, Y. Han, Q. Xu and X. Li

A Low-Cost Concurrent Error Detection Technique for Processor Control Logic [p. 897]

R. Vemu, A. Jas, J.A. Abraham, S. Patil and R. Galivanche

Approximate Logic Circuits for Low Overhead, Non-Intrusive Concurrent Error Detection [p. 903]

M.R. Choudhury and K. Mohanram

7.6: Safety-Driven Embedded Systems Design

Logical Reliability of Interacting Real-Time Tasks [p. 909]

K. Chatterjee, A. Ghosal, T.A. Henzinger, D. Iercan, C.M. Kirsch, C. Pinello and A. Sangiovanni-Vincentelli

Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints [p. 915]

V. Izosimov, P. Pop, P. Eles and Z. Peng

Tool Support for Incremental Failure Mode and Effects Analysis of Component-Based Systems [p. 921]

J. Elmqvist and S. Nadjm-Tehrani

Compositional Design of Isochronous Systems [p. 928]

J.-P. Talpin, J. Ouy, L. Besnard and P. Le Guernic

7.7: Hot Topic - Quantitative Productivity Measurement in IC Design

Quantitative Productivity Measurement in IC Design [p. 934]

F. Badstübner and A. Vörg

Determining the Technical Complexity of Integrated Circuits [p. 935]

P. Leppelt and E. Barke

Qualitative and Quantitative Analysis of IC Designs [p. 935]

S. Häusler, F. Poppen, K. Hausmann, A. Hahn and W. Nebel

Capturing and Analyzing IC Design Productivity Metrics [p. 936]

J. Young

Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits [p. 937]

K. Weinberger, S. Bulach and W. Rosenstiel

Optimization of Design Flows for Multi-Core x86 Microprocessors in 45 and 32nm Technologies under Productivity Considerations [p. 938]

H.-J. Brand

8.1: Dependable Computing in the Face of Scaled CMOS Challenges (Dependable Embedded Systems Day)

Implications of Technology Trends on System Dependability [p. 940]

J.A. Abraham

Globally Optimized Robust Systems to Overcome Scaled CMOS Challenges [p. 941]

S. Mitra

Software Protection Mechanisms for Dependable Systems [p. 947]

U. Wappler and M. Müller

8.2: Invited Industrial Session - Industrial System Designs in Information Technologies

Subsystem Exchange in a Concurrent Design Process Environment [p. 953]

M. Strik, A. Gonier and P. Williams

Cooperative Safety: Combination Of Mutiple Technologies [p. 959]

R. Panazzi, P. Capozio, M. Duncan, A. Scuderi, M. Siti and E. Merli

System Performance Optimization Methodology for Infineon's 32-Bit Automotive Microcontroller Architecture [p. 962]

A. Mayer and F. Hellwig

8.3: Power-Aware Circuit and Process Techniques

Process Variation Tolerant Design Through a Placement-Aware Multiple Voltage Island Design Style [p. 967]

S. Bonesi, D. Bertozzi, L. Benini and E. Macii

Optimal MTCMOS Reactivation under Power Supply Noise and Performance Constraints [p. 973]

A. Calimera, L. Benini and E. Macii

A Single-supply True Voltage Level Shifter [p. 979]

R. Garg, G. Mallarapu, S.P. Khatri

Clock Distribution Scheme Using Coplanar Transmission Lines [p. 985]

V.H. Cordero and S.P. Khatri

8.4: Multicore Design Solutions

Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors [p. 991]

A.M. Molnos, M.J.M. Heijligers and S.D. Cotofana

Comparison of Memory Write Policies for NoC Based Multicore Cache Coherent Systems [p. 997]

P. Guironnet de Massas and F. Pétrot

Serialized Asynchronous Links for NoC [p. 1003]

S. Ogg, E. Valli, B. Al-Hashimi, A. Yakovlev, C. D'Alessandro and L. Benini

8.5: Innovative and Emerging Technologies, Systems and Applications

Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits [p. 1009]

J. Zhang, N.P. Patil and S. Mitra

Quantified Synthesis of Reversible Logic [p. 1015]

R. Wille, H.M. Le, G.W. Dueck and D. Groβe

Adaptive Simulation for Single-Electron Devices [p. 1021]

N. Allec, R. Knobel and L. Shang

OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks [p. 1027]

F.J. Rincón, M. Paselli, J. Recas, Q. Zhao, M. Sánchez Eles, D. Atienza, J. Penders and G. De Micheli

8.6: New Real-Time Scheduling Approaches and their Applications

Improvements in Polynomial-Time Feasibility Testing for EDF [p. 1033]

A. Masrur, S. Drössler and G. Färber

A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications [p. 1039]

A. Tumeo, M. Branca, L. Camerini, M. Ceriani, M. Monchiero, G. Palermo, F. Ferrandi and D. Sciuto

An Application-Based EDF Scheduler For OSEK/VDX [p. 1045]

C. Diederichs, U. Margull, F. Slomka and G. Wirrer

Time Properties of the BuST Protocol under the NPA Budget Allocation Scheme [p. 1051]

G. Franchino, G. Buttazzo and T. Facchinetti

8.7: High-Level Synthesis and IP Protection

Simultaneous FU and Register Binding Based on Network Flow Method [p. 1057]

J. Cong and J. Xu

A Variation Aware High Level Synthesis Framework [p. 1063]

F. Wang, G. Sun and Y. Xie

EPIC: Ending Piracy of Integrated Circuits [p. 1069]

J.A. Roy, F. Koushanfar and I.L. Markov

IP4 Interactive Presentations

VLSI Implementation of SISO Arithmethic Decoder FOR Joint Source Channel Coding [p. 1075]

S. Zezza and G. Masera

Error Detection/Correction in DNA Algorithmic Self-Assembly [p. 1079]

S. Frechette and F. Lombardi

Temperature-Aware Voltage Selection for Energy Optimization [p. 1083]

M. Bao, A. Andrei, P. Eles and Z. Peng

A Fast Approximation Algorithm for MIN-ONE SAT [p. 1087]

L. Fang and M.S. Hsiao

Deep Submicro Interconnect Timing Model with Quadratic Random Variable Analysis [p. 1091]

J.-K. Zeng and C.-P. Chen

An Efficient Algorithm for Free Resources Management on the FPGA [p. 1095]

Y. Lu, T. Marconi, G. Gaydadjiev and K. Bertels

Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits [p. 1099]

H. Yoshida and M. Fujita

Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs [p. 1103]

S. Bahukudumbi, K. Chakrabarty and R. Kacprowicz

CARbridge, Reduction of System Complexity by Standardization of the System-Basis-Chips for Automotive Applications [p. 1107]

P. Scheer, E. Schmidt and S. Burges

9.1.1: Synthesis of Dependable Embedded Systems (Dependable Embedded Systems Day)

Specification and Design Considerations for Reliable Embedded Systems [p. 1111]

A. Israr and S. Huss

Synthesis of Fault-Tolerant Embedded Systems [p. 1117]

P. Eles, V. Izosimov, P. Pop and Z. Peng

9.1.2: LUNCH TIME KEYNOTE - (Dependable Embedded Systems Day)

Reliable Services in an Imperfect World [p. 1123]

H. Kopetz

9.2: HOT TOPIC - The Memory Challenge in NoC Based Systems

Video Processing Requirements on SoC Infrastructures [p. 1124]

P. van der Wolf and T. Henriksson

Memory Technology for Extended Large-Scale Integration in Future Electronics Applications [p. 1126]

D. Pamunuwa

Memory-aware NoC Exploration and Design [p. 1128]

N. Dutt

9.3: Timing Issues in Logic Synthesis

Incremental Criticality and Yield Gradients [p. 1130]

J. Xiong, V. Zolotov and C. Visweswariah

Latch Modeling for Statistical Timing Analysis [p. 1136]

S.X. Shi, A. Ramalingam, D. Wang and D.Z. Pan

Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis [p. 1142]

A. Mokhov and A. Yakovlev

9.4: Secured Systems

Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor [p. 1148]

J. Thoguluva, A. Raghunathan and S.T. Chakradhar

Operating System Controlled Processor-Memory Bus Encryption [p. 1154]

X. Chen, R.P. Dick and A. Choudhary

An Efficient FPGA Implementation of Principle Component Analysis Based Network Intrusion Detection System [p. 1160]

A. Das, S. Misra, S. Joshi, J. Zambreno, G. Memik and A. Choudhary

9.5: Test Generation for New Technologies

A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy [p. 1166]

I. Pomeranz and S.M. Reddy

Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation [p. 1172]

J. Lee, S. Narayan, M. Kapralos and M. Tehranipoor

Multi-Vector Tests: A Path to Perfect Error-Rate Testing [p. 1178]

S. Shahidi and S. Gupta

iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing [p. 1184]

J. Li, Q. Xu, Y. Hu and X. Li

9.6: Memory-Centric Code Optimisation

Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors [p. 1190]

S. Park, A. Shrivastava and Y. Paek

Instruction Cache Energy Saving Through Compiler Way-Placement [p. 1196]

T.M. Jones, S. Bartolini, B. De Bus, J. Cavazos and M.F.P. O'Boyle

Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints [p. 1202]

C.J. Xue, E.H.-M. Sha, Z. Shao and M. Qiu

9.7: Acceleration of Reconfigurable Applications

Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications [p. 1208]

A.C.S. Beck, M.B. Rutzig, G. Gaydadjiev and L. Carro

Automatic Selection of Application-Specific Reconfigurable Processor Extensions [p. 1214]

C. Wolinski and K. Kuchcinski

An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications [p. 1220]

S. Saha, J. Schlessman, S. Puthenpurayil, S.S. Bhattacharyya and W. Wolf

10.1: Dependability Aspects (Dependable Embedded Systems Day)

Dependability for High-Tech Systems: An Industry-as-Laboratory Approach [p. 1226]

E. Brinksma and J. Hooman

10.2: Application Mapping onto NoCs and Flow Control

User-Aware Dynamic Resource Allocation in Networks-on-Chip [p. 1232]

C.-L. Chou and R. Marculescu

Minimizing Virtual Channel Buffer for Routers in On-Chip Communication Architectures [p. 1238]

M.A. Al Faruque and J. Henkel

An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication [p. 1244]

W.-C. Kwon, S.-M. Hong, S. Yoo, B. Min, K.-M. Choi, S.-K. Eo

10.3: Arithmetic and Logic Processing

Variable Latency Speculative Adder: A New Paradigm for Arithmetic Circuit Design [p. 1250]

A.K. Verma, P. Brisk and P. Ienne

Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming [p. 1256]

H. Parandeh-Afshar, P. Brisk and P. Ienne

An Adaptable FPGA-Based System for Regular Expression Matching [p. 1262]

I. Bonesana, M. Paolieri and M.D. Santambrogio

Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems [p. 1268]

M.N. Velev and P. Gao

10.4: Security Building Blocks

Defeating Classical Hardware Countermeasures: A New Processing for Side Channel Analysis [p. 1274]

D. Real, C. Canovas, J. Clediere, M. Drissi and F. Valette

Power Balanced Gates Insensitive to Routing Capacitance Mismatch [p. 1280]

K.J. Kulikowski, V. Venkatarama, Z. Wang and A. Taubin

On Analysis and Synthesis of (n,k)-Non-Linear Feedback Shift Registers [p. 1286]

E. Dubrova, M. Teslenko and H. Tenhunen

FPGA Design for Algebraic Tori Based Public Key Cryptography [p. 1292]

J. Fan, L. Batina, K. Sakiyama and I. Verbauwhede

10.5: A Smorgardsbord of Test

Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation [p. 1298]

H.F. Ko and N. Nicolici

Functional Self-Testing for Bus-Based Symmetric Multiprocessors [p. 1304]

A. Apostolakis, D. Gizopoulos, M. Psarakia and A. Paschalis

Theoretical and Practical Aspects of IDDQ Settling - Impact on Measurement Timing and Quality [p. 1310]

B. Straka, H. Manhaeve, J. Brenkus and S. Kerckenaere

10.6: HOT TOPIC - Analogue: How to Survive in the Era of Nano CMOS

Advanced Analog Filters for Telecommunications [p. 1316]

M. De Matteis, S. D'Amico and A. Baschirotto

Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies [p. 1322]

G. Gielen, P. DeWit, E. Maricau, J. Loeckx, J. Martín-Martínez, B. Kaczer, G. Groeseneken, R. Rodríguez and M. Nafría

Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces [p. 1328]

C. Guiducci, A. Schmid, F.K. Gürkaynak and Y. Leblebici

10.7: Reconfigurable Architectures and Run-Time Optimisations

High-Level Modeling and Exploration of Coarse-Grained Re-Configurable Architectures [p. 1334]

A. Chattopadhyay, X. Chen, H. Ishebabi, R. Leupers, G. Ascheid and H. Meyr

Scalable Architecture for On-Chip Neural Network Training Using Swarm Intelligence [p. 1340]

A. Farmahini-Farahani, S.M. Fakhraie and S. Safari

Intelligent Merging OnLine Task Placement Algorithm for Partially Reconfigurable Systems [p. 1346]

T. Marconi, Y. Lu, K. Bertels and G. Gaydadjiev

Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]

A. Deledda, C. Mucci, A. Vitkovski, M. Kuehnle, F. Ries, M. Huebner, J. Becker, P. Bonnot, A. Grasset, P. Millet, M. Coppola, L. Pieralisi, R. Locatelli, G. Maruccia, F. Campi and T. DeMarco

IP5 Interactive Presentations

Automated Dynamic Throughput-Constrained Structural-Level Pipelining in Streaming Applications [p. 1358]

M. Muir, T. Arslan and I. Lindsay

Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme [p. 1362]

F. Wolff, C. Papachristou, S. Bhunia and R.S. Chakraborty

Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects [p. 1366]

T. Yoneda and H. Fujiwara

De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs [p. 1370]

M. Hosseinabady, M.R. Kakoee, J. Mathew and D.K. Pradhan

Adaptive Filesystem Compression for Embedded Systems [p. 1374]

L.S. Bai, H. Lekatsas and R.P. Dick

Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits [p. 1378]

D.Y. Feinstein, M.A. Thornton and D.M. Miller

TinyTimber, Reactive Objects in C for Real-Time Embedded Systems [p. 1382]

P. Lindgren, J. Eriksson, S. Aittamaa and J. Nordlander

Dynamic Task Allocation Strategies in MPSoC for Soft Real-Time Applications [p. 1386]

E. Wenzel Brião, D. Barcelos, F. Rech Wagner

Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications [p. 1390]

P. Nuzzo, C. Nani, S. Saponara, L. Fanucci and G. Van der Plas

11.1: PANEL SESSION - New Directions and Challenges (Dependable Embedded Systems Day)

Dependable Embedded Systems Day Panel: Issues and Challenges in Dependable Embedded Systems [p. 1394]

Panelists: J. Abraham, S. Poledna, A. Mendelson and S. Mitra

11.2: Routing and Link Design

Multicast Parallel Pipeline Routing Architecture FOR Network-on-Chip [p. 1396]

F.A. Samman, T. Hollstein and M. Glesner

Variation Tolerant NoC Design by Means of Self-Calibrating Links [p. 1402]

S. Medardoni, M. Lajolo and D. Bertozzi

BARP- A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs [p. 1408]

P. Lotfi-Kamran, M. Daneshtalab, C. Lucas and Z. Navabi

Developing Mesochronous Synchronizers to Enable 3D NoCs [p. 1414]

I. Loi, F. Angiolini and L. Benini

11.3: Microarchitecture Analysis and Optimisation

Memory Organization with Multi-Pattern Parallel Accesses [p. 1420]

A. Vitkovski, G. Kuzmanov and G. Gaydadjiev

CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and Its Application to Instruction Caches [p. 1426]

M. Kleanthous and Y. Sazeides

MAGELLAN: A Search and Machine Learning-Based Framework for Fast Multi-Core Design Space Exploration and Optimization [p. 1432]

S. Kahng and R. Kumar

Process Variation Aware Issue Queue Design [p. 1438]

R. K and M. Mutyam

11.4: System Implementations for Network and Cryptography

Implementation of Parallel LFSR-Based Applications on an Adaptive DSP Featuring a Pipelined Configurable Gate Array [p. 1444]

C. Mucci, L. Vanzolini, I. Mirimin, D. Gazzola, A. Deledda, S. Goller, J. Knaeblein, A. Schneider, L. Ciccarelli and F. Campi

GMDS: Hardware Inplementation of Novel Real Output Queuing Architecture [p. 1450]

R. Arteaga, F. Tobajas, R. Esper-Chain, V. de Armas and R. Sarmiento

Front End Device for Content Networking [p. 1456]

J. Buboltz and T. Kocak

Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography [p. 1462]

M. Purnaprajna, C. Puttmann, M. Porrmann

11.5: Jitter Test and Fault Diagnosis

Digital Bit Stream Jitter Testing Using Jitter Expansion [p. 1468]

H. Choi and A. Chatterjee

A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution [p. 1474]

I. Pomeranz and S.M. Reddy

A Design-for-Diagnosis Technique for SRAM Write Drivers [p. 1480]

A. Ney, P. Girard, S. Pravossoudovitch, A. Virazel, M. Bastian and V. Gouin

Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications [p. 1486]

D.C. Keezer, D. Minier and P. Ducharme

11.6: Software Synthesis and Embedded Code Generation

Retargetable Code Optimization for Predicated Execution [p. 1492]

M. Hohenauer, F. Engel, R. Leupers, G. Ascheid, H. Meyr, G. Bette and B. Singh

Programming Shared Memory Multiprocessors with Deterministic Message-Passing Concurrency: Compiling SHIM to Pthreads [p. 1498]

S.A. Edwards, N. Vasudevan and O. Tardieu

Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams [p. 1504]

R. Lublinerman and S. Tripakis

ezRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis [p. 1510]

F. Cruz, R. Barreto, L. Cordeiro and P. Maciel

11.7: HOT TOPIC - 3D Integration or How to Scale in the 21st Century

3D Integration or How to Scale in the 21st Century [p. 1516]

Presenters: L. Benini, D. Keitel-Schulz, N. Checka [p. 1516]