DATE 2008 AUTHOR INDEX

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

A

Abdi, S.
Cycle-approximate Retargetable Performance Estimation at the Transaction Level [p. 3]
Aboshady, H.
Modeling and Refining Heterogeneous Systems with SystemC-AMS: Application to WSN [p. 134]
Abraham, J.
Dependable Embeded Systems Day Panel: Issues and Challenges in Dependable Embedded Systems [p. 1394]
Abraham, J.A.
A Low-Cost Concurrent Error Detection Technique for Processor Control Logic [p. 897]
Implications of Technology Trends on System Dependability [p. 940]
Acquaviva, A.
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures [p. 734]
Aguirre, M.
On the Design of Tunable Fault Tolerant Circuits on SRAM-Based FPGAs for Safety Critical Applications [p. 336]
Aitken, R.
PANEL - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm [p. 510]
Aittamaa, S.
TinyTimber, Reactive Objects in C for Real-Time Embedded Systems [p. 1382]
Al Faruque, M.A.
Minimizing Virtual Channel Buffer for Routers in On-Chip Communication Architectures [p. 1238]
Al-Hashimi, B. M.
Efficient Circuit-Level Modeling of Ballistic CNT Using Piecewise Non-Linear Approximation of Mobile Charge Density [p. 146]
Integrated Approach to Energy Harvester Mixed Technology Modeling and Performance Optimization [p. 704]
Serialized Asynchronous Links for NoC [p. 1003]
Ali, S.
A New Approach for Combining Yield and Performance in Behavioral Models for Analogue Integrated Circuits [p. 152]
Allam, O.
A Coarse-Grained Array Based Baseband Processor for 100mbps+ Software Defined Radio [p. 716]
Alles, M.
A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder [p. 456]
Allec, N.
Adaptive Simulation for Single-Electron Devices [p. 1021]
Alt, N.
Hardware/Software Architecture of an Algorithm for Vision-Based Real-Time Vehicle Detection in Dark Environments [p. 176]
Amelifard, B.
A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect [p. 568]
Amerijckx, C.
Industrial IP Integration Flows Based on IP-XACTTM Standards [p. 32]
Andrei, A.
Temperature-Aware Voltage Selection for Energy Optimization [p. 1083]
Angiolini, F.
Developing Mesochronous Synchronizers to Enable 3D NoCs [p. 1414]
Apostolakis, A.
Functional Self-Testing for Bus-Based Symmetric Multiprocessors [p. 1304]
Arons, T.
Efficient Symbolic Simulation of Low Level Software [p. 825]
Arslan, T.
Automated Dynamic Throughput-Constrained Structural-Level Pipelining in Streaming Applications [p. 1358]
Arteaga, R.
GMDS: Hardware Inplementation of Novel Real Output Queuing Architecture [p. 1450]
Arzel, F.
A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs [p. 740]
Ascheid, G.
High-Level Modeling and Exploration of Coarse-Grained Re-Configurable Architectures [p. 1334]
Retargetable Code Optimization for Predicated Execution [p. 1492]
Atienza, D.
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization [p. 110]
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures [p. 734]
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks [p. 1027]
Audisio, G.
Physical Architectures of Automotive Systems [p. 391]
Avnit, K.
A Formal Approach to the Protocol Converter Problem [p. 294]

B

Bacciarelli, L.
A Programmable and Low-EMI Integrated Half-Bridge Driver IN BCD Technology [p. 879]
Bacinschi, P.B.
Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation [p. 688]
An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs [p. 698]
Badaroglu, M.
Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment [p. 873]
Badel, S.
A Generic Standard Cell Design Methodology for Differential Circuit Styles [p. 843]
Badstübner, F.
Quantitative Productivity Measurement in IC Design [p. 934]
Bahukudumbi, S.
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs [p. 1103]
Bai, L.S.
Adaptive Filesystem Compression for Embedded Systems [p. 1374]
Balp, H.
Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components [p. 330]
Banerjee, K.
High-Frequency Mutual Impedance Extraction of VLSI Interconnects in the Presence of a Multi-Layer Conducting Substrate [p. 426]
Bao, M.
Temperature-Aware Voltage Selection for Energy Optimization [p. 1083]
Barcelos, D.
Dynamic Task Allocation Strategies in MPSoC for Soft Real-Time Applications [p. 1386]
Barke, E.
Determining the Technical Complexity of Integrated Circuits [p. 935]
Barragán, M.J.
Practical Implementation of a Network Analyzer for Analog BIST Applications [p. 80]
Barreto, R.
ezRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis [p. 1510]
Bartolini, S.
Instruction Cache Energy Saving Through Compiler Way-Placement [p. 1196]
Baschirotto, A.
Advanced Analog Filters for Telecommunications [p. 1316]
Basten, T.
Parametric Throughput Analysis of Synchronous Data Flow Graphs [p. 116]
Bastian, M.
A Design-for-Diagnosis Technique for SRAM Write Drivers [p. 1480]
Batcher, K.W.
Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems [p. 260]
Batina, L.
FPGA Design for Algebraic Tori Based Public Key Cryptography [p. 1292]
Bauer, L.
Run-Time System for an Extensible Embedded Processor with Dynamic Instruction Set [p. 752]
Beck, A.C.S.
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications [p. 1208]
Becker, B.
Resistive Bridging Fault Simulation of Industrial Circuits [p. 628]
Becker, J.
Cost - And Power Optimized FPGA Based System Integration: Methodologies and Integration of a Low-Power Capacity- Based Measurement Application on Xilinx FPGAs [p. 50]
A System Architecture for Reconfigurable Trusted Platforms [p. 541]
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms [p. 604]
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Beeby, S.P.
Integrated Approach to Energy Harvester Mixed Technology Modeling and Performance Optimization [p. 704]
Beenaert, D.
ARTEMIS and ENIAC Joint Undertakings: A New Approach to Conduct Research in Europe [p. 658]
Beilleau, N.
Modeling and Refining Heterogeneous Systems with SystemC-AMS: Application to WSN [p. 134]
Bekooij, M.
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip [p. 300]
Bekooij, M.J.G.
Computation of Buffer Capacities for Throughput Constrained and Data Dependent Inter-Task Communication [p. 640]
Ben Gaid, M.E.M.
A Methodology for Improving Software Design Lifecycle in Embedded Control Systems [p. 533]
Benini, L.
An Efficient Solar Energy Harvester for Wireless Sensor Nodes [p. 104]
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization [p. 110]
Robust and Low Complexity Rate Control for Solar Powered Sensors [p. 230]
A Scalable Algorithmic Framework FOR Row-Based Power-Gating [p. 379]
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures [p. 734]
Process Variation Tolerant Design Through a Placement-Aware Multiple Voltage Island Design Style [p. 967]
Optimal MTCMOS Reactivation under Power Supply Noise and Performance Constraints [p. 973]
Serialized Asynchronous Links for NoC [p. 1003]
Developing Mesochronous Synchronizers to Enable 3D NoCs [p. 1414]
3D Integration or How to Scale in the 21st Century [p. 1516]
Bernardi, P.
A Novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers [p. 194]
Bertacco, V.
Random Stimulus Generation Using Entropy and XOR Constraints [p. 664]
MCjammer: Adaptive Verification for Multi-Core Designs [p. 670]
Bertels, K.
An Efficient Algorithm for Free Resources Management on the FPGA [p. 1095]
Intelligent Merging OnLine Task Placement Algorithm for Partially Reconfigurable Systems [p. 1346]
Bertini, L.
Hot Wire Anemometric MEMs Sensor for Water Flow Monitoring [p. 342]
Bertozzi, D.
Process Variation Tolerant Design Through a Placement-Aware Multiple Voltage Island Design Style [p. 967]
Variation Tolerant NoC Design by Means of Self-Calibrating Links [p. 1402]
Besnard, L.
Compositional Design of Isochronous Systems [p. 928]
Bette, G.
Retargetable Code Optimization for Predicated Execution [p. 1492]
Beutel, J.
Software for Wireless Networked Embedded Systems [p. 372]
Bhattacharyya, S.S.
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications [p. 1220]
Bhatti, N.K.
Physically-Aware N-Detect Test Pattern Selection [p. 634]
Bhunia, S.
Harvesting Wasted Heat in a Microprocessor Using Thermo-Electric Generators: Modeling, Analysis And Measurement [p. 98]
Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction [p. 373]
Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme [p. 1362]
Bin, B.
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution [p. 242]
Bingesser, M.
Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement [p. 868]
Blaauw, D.
Transistor-Specific Delay Modeling for SSTA [p. 592]
Blanton, R.D.S.
Automated Testability Enhancements for Logic Brick Libraries [p. 480]
Physically-Aware N-Detect Test Pattern Selection [p. 634]
Blume, H.
Design Flow for Embedded FPGAs Based on a Flexible Architecture Template [p. 56]
Bombieri, N.
Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation [p. 15]
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces [p. 396]
Bonesana, I.
An Adaptable FPGA-Based System for Regular Expression Matching [p. 1262]
Bonesi, S.
Process Variation Tolerant Design Through a Placement-Aware Multiple Voltage Island Design Style [p. 967]
Bonnot, P.
Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA [p. 610]
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Bonny, T.
Instruction Re-Encoding Facilitating Dense Embedded Code [p. 770]
Bouali, A.
PANEL - The Future Car: Technology, Methods and Tools [p. 812]
Boucheneb, H.
Semantics for Model-Based Validation of Continuous/Discrete Systems [p. 498]
Bouchhima, F.
Semantics for Model-Based Validation of Continuous/Discrete Systems [p. 498]
Bougard, B.
Optimizating Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures [p. 444]
Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications [p. 598]
A Coarse-Grained Array Based Baseband Processor for 100mbps+ Software Defined Radio [p. 716]
Scenario-Based Fixed-Point Data Format Refinement to Enable Energy-Scalable Software Defined Radios [p. 722]
Boyd, S.
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization [p. 110]
Branca, M.
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications [p. 1039]
Brand, H.-J.
Optimization of Design Flows for Multi-Core x86 Microprocessors in 45 and 32nm Technologies under Productivity Considerations [p. 938]
Brenkus, J.
Theoretical and Practical Aspects of IDDQ Settling - Impact on Measurement Timing and Quality [p. 1310]
Brewer, F.
Synthesizing Synchronous Elastic Flow Networks [p. 306]
Brinksma, E.
Dependability for High-Tech Systems: An Industry-as-Laboratory Approach [p. 1226]
Brisk, P.
Variable Latency Speculative Adder: A New Paradigm for Arithmetic Circuit Design [p. 1250]
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming [p. 1256]
Brisolara, L.B.
Using UML as Front-End for Heterogeneous Software Code Generation Strategies [p. 504]
Brown, A.
A New Approach for Combining Yield and Performance in Behavioral Models for Analogue Integrated Circuits [p. 152]
Brown, J.G.
Automated Testability Enhancements for Logic Brick Libraries [p. 480]
Brunelli, D.
An Efficient Solar Energy Harvester for Wireless Sensor Nodes [p. 104]
Robust and Low Complexity Rate Control for Solar Powered Sensors [p. 230]
Buboltz, J.
Front End Device for Content Networking [p. 1456]
Bulach, S.
Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits [p. 937]
Burges, S.
CARbridge, Reduction of System Complexity by Standardization of the System-Basis-Chips for Automotive Applications [p. 1107]
Buttazzo, G.
Time Properties of the BuST Protocol under the NPA Budget Allocation Scheme [p. 1051]
Buttu, M.
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures [p. 734]

C

Calimera, A.
Optimal MTCMOS Reactivation under Power Supply Noise and Performance Constraints [p. 973]
Camerini, L.
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications [p. 1039]
Campi, F.
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Implementation of Parallel LFSR-Based Applications on an Adaptive DSP Featuring a Pipelined Configurable Gate Array [p. 1444]
Canovas, C.
Defeating Classical Hardware Countermeasures: A New Processing for Side Channel Analysis [p. 1274]
Capozio, P.
Cooperative Safety: Combination Of Mutiple Technologies [p. 959]
Carro, L.
Using UML as Front-End for Heterogeneous Software Code Generation Strategies [p. 504]
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications [p. 1208]
Carta, S.
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures [p. 734]
Catthoor, F.
Optimizating Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures [p. 444]
Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications [p. 598]
Scenario-Based Fixed-Point Data Format Refinement to Enable Energy-Scalable Software Defined Radios [p. 722]
Cavazos, J.
Instruction Cache Energy Saving Through Compiler Way-Placement [p. 1196]
Ceriani, M.
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications [p. 1039]
Certner, O.
A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs [p. 740]
Chakrabarty, K.
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns [p. 188]
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs [p. 1103]
Chakraborty, A.
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices [p. 849]
Chakraborty, R.S.
Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme [p. 1362]
Chakradhar, S.T.
Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor [p. 1148]
Chandra, A.
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction [p. 462]
Chantem, T.
Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs [p. 288]
Charlier, O.
Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment [p. 873]
Chatterjee, A.
Digital Bit Stream Jitter Testing Using Jitter Expansion [p. 1468]
Chatterjee, K.
Logical Reliability of Interacting Real-Time Tasks [p. 909]
Chattopadhyay, A.
Built-In Clock Skew System for On-Line Debug and Repair [p. 248]
High-Level Modeling and Exploration of Coarse-Grained Re-Configurable Architectures [p. 1334]
Chaves, R.
Merged Computation for Whirlpool Hashing [p. 272]
Checka, N.
3D Integration or How to Scale in the 21st Century [p. 1516]
Chen, C.-P.
Deep Submicro Interconnect Timing Model with Quadratic Random Variable Analysis [p. 1091]
Chen, F.-W.
Wire Sizing Alternative - An Uniform Dual-Rail Routing Architecture [p. 796]
Chen, H.
A Novel Technique for Improving Temperature Independency of Ring-ADC [p. 694]
Chen, X.
Operating System Controlled Processor-Memory Bus Encryption [p. 1154]
High-Level Modeling and Exploration of Coarse-Grained Re-Configurable Architectures [p. 1334]
Chen, Z.-Y.
Instruction Set Extension Exploration in Multiple-Issue Architecture [p. 764]
Cheng, C.-K.
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network [p. 537]
Cheng, X.
Simulation-Directed Invariant Mining for Software Verification [p. 682]
Cheung, P. Y. K.
Using Reconfigurable Logic to Optimise GPU Memory Accesses [p. 44]
Choi, H.
Digital Bit Stream Jitter Testing Using Jitter Expansion [p. 1468]
Choi, K.-M.
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution [p. 242]
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication [p. 1244]
Chopra, K.
Transistor-Specific Delay Modeling for SSTA [p. 592]
Chou, C.-L.
User-Aware Dynamic Resource Allocation in Networks-on-Chip [p. 1232]
Choudhary, A.
Operating System Controlled Processor-Memory Bus Encryption [p. 1154]
An Efficient FPGA Implementation of Principle Component Analysis Based Network Intrusion Detection System [p. 1160]
Choudhury, M.R.
Approximate Logic Circuits for Low Overhead, Non-Intrusive Concurrent Error Detection [p. 903]
Chua-Eoan, L.
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network [p. 537]
Chung, C.-P.
Instruction Set Extension Exploration in Multiple-Issue Architecture [p. 764]
Ciccarelli, L.
Implementation of Parallel LFSR-Based Applications on an Adaptive DSP Featuring a Pipelined Configurable Gate Array [p. 1444]
Claus, C.
Hardware/Software Architecture of an Algorithm for Vision-Based Real-Time Vehicle Detection in Dark Environments [p. 176]
Clediere, J.
Defeating Classical Hardware Countermeasures: A New Processing for Side Channel Analysis [p. 1274]
Cline, B.
Transistor-Specific Delay Modeling for SSTA [p. 592]
Cloth, L.
Quantitative Evaluation in Embedded System Design: Predicting Battery Lifetime in Mobile Devices [p. 90]
Colas-Bigey, F.
SystemC-Based Modeling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder [p. 128]
Cong, J.
Simultaneous FU and Register Binding Based on Network Flow Method [p. 1057]
Cope, B.
Using Reconfigurable Logic to Optimise GPU Memory Accesses [p. 44]
Coppola, M.
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Cordeiro, L.
ezRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis [p. 1510]
Cordero, V.H.
Clock Distribution Scheme Using Coplanar Transmission Lines [p. 985]
Cornet, J.
A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip [p. 9]
Coste, N.
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures [p. 88]
Cotofana, S.D.
Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors [p. 991]
Cruz, F.
ezRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis [p. 1510]

D

D'Amico, S.
Advanced Analog Filters for Telecommunications [p. 1316]
D'Alessandro, C.
Serialized Asynchronous Links for NoC [p. 1003]
Damm, W.
Software Components for Reliable Automotive Systems [p. 549]
Daneshtalab, M.
BARP- A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs [p. 1408]
Das, A.
An Efficient FPGA Implementation of Principle Component Analysis Based Network Intrusion Detection System [p. 1160]
D'Ascoli, F.
Hot Wire Anemometric MEMs Sensor for Water Flow Monitoring [p. 342]
A Programmable and Low-EMI Integrated Half-Bridge Driver IN BCD Technology [p. 879]
David, A.
A Game-Theoretic Approach to Real-Time System Testing [p. 486]
de Armas, V.
GMDS: Hardware Inplementation of Novel Real Output Queuing Architecture [p. 1450]
De Bus, B.
Instruction Cache Energy Saving Through Compiler Way-Placement [p. 1196]
de Kock, E.
Industrial IP Integration Flows Based on IP-XACTTM Standards [p. 32]
de la Rosa, J.M.
A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications [p. 862]
De Marinis, M.
Hot Wire Anemometric MEMs Sensor for Water Flow Monitoring [p. 342]
A Programmable and Low-EMI Integrated Half-Bridge Driver IN BCD Technology [p. 879]
De Matteis, M.
Advanced Analog Filters for Telecommunications [p. 1316]
De Micheli, G.
Designing Micro/Nano Systems for a Safer and Healthier Tomorrow [p. 1]
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization [p. 110]
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures [p. 734]
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks [p. 1027]
de Paoli, S.
Industrial IP Integration Flows Based on IP-XACTTM Standards [p. 32]
De Sutter, B.
A Coarse-Grained Array Based Baseband Processor for 100mbps+ Software Defined Radio [p. 716]
De Venuto, D.
PWM-Based Test Stimuli Generation for BIST of High Resolution Sigma-Delta ADCS [p. 284]
Decabooter, G.
Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment [p. 873]
Deganello, N.
Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation [p. 15]
Dekneuvel, E.
A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design [p. 804]
del Prado Pavon, J.
A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design [p. 804]
del Río, R.
A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications [p. 862]
Deledda, A.
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Implementation of Parallel LFSR-Based Applications on an Adaptive DSP Featuring a Pipelined Configurable Gate Array [p. 1444]
DeMarco, T.
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
DeWit, P.
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies [p. 1322]
Di Natale, M.
Physical Architectures of Automotive Systems [p. 391]
Software Components for Reliable Automotive Systems [p. 549]
Methods, Tools and Standards for the Analysis and Evaluation of Modern Automotive Architectures [p. 659]
Diaconescu, D.
Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM Devices [p. 776]
Dick, R.P.
Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs [p. 288]
Operating System Controlled Processor-Memory Bus Encryption [p. 1154]
Adaptive Filesystem Compression for Embedded Systems [p. 1374]
Diederichs, C.
An Application-Based EDF Scheduler For OSEK/VDX [p. 1045]
Dömer, R.
Introducing Preemptive Scheduling in Abstract RTOS Models Using Result Oriented Modeling [p. 122]
Dong, M.
Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-Based Integration [p. 268]
Dorn, R.
Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement [p. 868]
Drach, N.
A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs [p. 740]
Drechsler, R.
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs [p. 206]
Automatic Generation of Complex Properties for Hardware Designs [p. 545]
Drissi, M.
Defeating Classical Hardware Countermeasures: A New Processing for Side Channel Analysis [p. 1274]
Drössler, S.
Improvements in Polynomial-Time Feasibility Testing for EDF [p. 1033]
D'Silva, V.
A Formal Approach to the Protocol Converter Problem [p. 294]
Duan, C.
Energy Efficient and High Speed On-Chip Ternary Bus [p. 515]
Dubrova, E.
On Analysis and Synthesis of (n,k)-Non-Linear Feedback Shift Registers [p. 1286]
Ducharme, P.
Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications [p. 1486]
Dueck, G.W.
Quantified Synthesis of Reversible Logic [p. 1015]
Duncan, M.
Cooperative Safety: Combination Of Mutiple Technologies [p. 959]
Dunkels, A.
Software for Wireless Networked Embedded Systems [p. 372]
Dupont, S.
A Coarse-Grained Array Based Baseband Processor for 100mbps+ Software Defined Radio [p. 716]
Dutt, N.
Constraint Refinement for Online Verifiable Cross-Layer System Adaptation [p. 646]
Memory-aware NoC Exploration and Design [p. 1128]

E

Eberle, W.
A Scalable Low-Power Digital Communication Network Architecture and an Automated Design Path for Controlling the Analog/RF Part of SDR Transceivers [p. 710]
Ecker, W.
Industrial IP Integration Flows Based on IP-XACTTM Standards [p. 32]
Edelin, G.
Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA [p. 610]
Edwards, S.A.
Programming Shared Memory Multiprocessors with Deterministic Message-Passing Concurrency: Compiling SHIM to Pthreads [p. 1498]
Einwich, K.
Modeling and Refining Heterogeneous Systems with SystemC-AMS: Application to WSN [p. 134]
Eles, P.
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns [p. 188]
A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems [p. 556]
Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints [p. 915]
Temperature-Aware Voltage Selection for Energy Optimization [p. 1083]
Synthesis of Fault-Tolerant Embedded Systems [p. 1117]
Elm, M.
Scan Chain Organization for Embedded Diagnosis [p. 468]
Elmqvist, J.
Tool Support for Incremental Failure Mode and Effects Analysis of Component-Based Systems [p. 921]
Elster, E.
Efficient Symbolic Simulation of Low Level Software [p. 825]
Engel, F.
Retargetable Code Optimization for Predicated Execution [p. 1492]
Engelke, P.
Resistive Bridging Fault Simulation of Industrial Circuits [p. 628]
Eo, S.-K.
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution [p. 242]
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication [p. 1244]
Eriksson, J.
TinyTimber, Reactive Objects in C for Real-Time Embedded Systems [p. 1382]
Ernst, R.
Modeling Event Stream Hierarchies with Hierarchical Event Models [p. 492]
Methods, Tools and Standards for the Analysis and Evaluation of Modern Automotive Architectures [p. 659]
Esper-Chain, R.
GMDS: Hardware Inplementation of Novel Real Output Queuing Architecture [p. 1450]

F

Facchinetti, T.
Time Properties of the BuST Protocol under the NPA Budget Allocation Scheme [p. 1051]
Färber, G.
Improvements in Polynomial-Time Feasibility Testing for EDF [p. 1033]
Fakhraie, S.M.
Scalable Architecture for On-Chip Neural Network Training Using Swarm Intelligence [p. 1340]
Fan, J.
FPGA Design for Algebraic Tori Based Public Key Cryptography [p. 1292]
Fang, L.
A Fast Approximation Algorithm for MIN-ONE SAT [p. 1087]
Fanucci, L.
Hot Wire Anemometric MEMs Sensor for Water Flow Monitoring [p. 342]
A Programmable and Low-EMI Integrated Half-Bridge Driver IN BCD Technology [p. 879]
Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications [p. 1390]
Farmahini-Farahani, A.
Scalable Architecture for On-Chip Neural Network Training Using Swarm Intelligence [p. 1340]
Fatemi, H.
A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect [p. 568]
Fei, Y.
Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency [p. 758]
Feinstein, D.Y.
Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits [p. 1378]
Fennel, H.
PANEL - The Future Car: Technology, Methods and Tools [p. 812]
Fernández Villena, J.
SPARE - A Scalable Algorithm for Passive, Structure Preserving, Parameter-Aware Model Order Reduction [p. 586]
Ferrandi, F.
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications [p. 1039]
Ferrari, A.
Physical Architectures of Automotive Systems [p. 391]
Fettweis, G.
A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs [p. 780]
Fey, G.
Automatic Generation of Complex Properties for Hardware Designs [p. 545]
Forest, T.
Physical Architectures of Automotive Systems [p. 391]
Forliti, M
A Programmable and Low-EMI Integrated Half-Bridge Driver IN BCD Technology [p. 879]
Fouilliart, A.-M.
SystemC-Based Modeling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder [p. 128]
Franchino, G.
Time Properties of the BuST Protocol under the NPA Budget Allocation Scheme [p. 1051]
Frank, E.
Methods, Tools and Standards for the Analysis and Evaluation of Modern Automotive Architectures [p. 659]
Frechette, S.
Error Detection/Correction in DNA Algorithmic Self-Assembly [p. 1079]
Freuer, J.
On the Verification of High-Order Constraint Compliance in IC Design [p. 26]
Fujita, M.
Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits [p. 1099]
Fujiwara, H.
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects [p. 1366]
Fummi, F.
Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation [p. 15]
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces [p. 396]
Fuβ, W.
Tailored Solutions for Safety-Installations in the Loetschberg Tunnel - A Project with Importance for the Trans-European Rail Traffic [p. 21]

G

Gaillat, G.
Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA [p. 610]
Gailliard, G.
Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components [p. 330]
Gajski, D.
Cycle-approximate Retargetable Performance Estimation at the Transaction Level [p. 3]
Galivanche, R.
A Low-Cost Concurrent Error Detection Technique for Processor Control Logic [p. 897]
Ganai, M.K.
Completeness in SMT-Based BMC for Software Programs [p. 831]
Gao, P.
Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems [p. 1268]
Garavel, H.
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures [p. 88]
Garg, R.
A Delay-Efficient Radiation-Hard Digital Design Approach Using CWSP Elements [p. 354]
A Single-supply True Voltage Level Shifter [p. 979]
Gauget, P.
Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA [p. 610]
Gaydadjiev, G.
An Efficient Algorithm for Free Resources Management on the FPGA [p. 1095]
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications [p. 1208]
Intelligent Merging OnLine Task Placement Algorithm for Partially Reconfigurable Systems [p. 1346]
Memory Organization with Multi-Pattern Parallel Accesses [p. 1420]
Gazzola, D.
Implementation of Parallel LFSR-Based Applications on an Adaptive DSP Featuring a Pipelined Configurable Gate Array [p. 1444]
Geilen, M.C.W.
Parametric Throughput Analysis of Synchronous Data Flow Graphs [p. 116]
Gerin, P.
Efficient Implementation of Native Software Simulation for MPSoC [p. 676]
Gerlach, J.
On the Verification of High-Order Constraint Compliance in IC Design [p. 26]
Ghamarian, A. H.
Parametric Throughput Analysis of Synchronous Data Flow Graphs [p. 116]
Gheorghe, L.
Semantics for Model-Based Validation of Continuous/Discrete Systems [p. 498]
Ghiasi, S.
Exact and Approximate Task Assignment Algorithms for Pipelined Software Synthesis [p. 746]
Ghosal, A.
Logical Reliability of Interacting Real-Time Tasks [p. 909]
Ghosh, S.
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking [p. 366]
Gide, L.
ARTEMIS and ENIAC Joint Undertakings: A New Approach to Conduct Research in Europe [p. 658]
Gielen, G.
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies [p. 1322]
Girard, P.
A Design-for-Diagnosis Technique for SRAM Write Drivers [p. 1480]
Gizopoulos, D.
Functional Self-Testing for Bus-Based Symmetric Multiprocessors [p. 1304]
Glas, B.
A System Architecture for Reconfigurable Trusted Platforms [p. 541]
Glaβ, M.
Symbolic Reliability Analysis and Optimization of ECU Networks [p. 158]
Glesner, M.
Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation [p. 688]
An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs [p. 698]
Multicast Parallel Pipeline Routing Architecture FOR Network-on-Chip [p. 1396]
Glinos, K.
ARTEMIS and ENIAC Joint Undertakings: A New Approach to Conduct Research in Europe [p. 658]
Goel, A.
Current Source Based Standard Cell Model for Accurate Signal Integrity and Timing Analysis [p. 574]
Goffioul, M.
A Scalable Low-Power Digital Communication Network Architecture and an Automated Design Path for Controlling the Analog/RF Part of SDR Transceivers [p. 710]
Goller, S.
Implementation of Parallel LFSR-Based Applications on an Adaptive DSP Featuring a Pipelined Configurable Gate Array [p. 1444]
Gonier, A.
Subsystem Exchange in a Concurrent Design Process Environment [p. 953]
Gouin, V.
A Design-for-Diagnosis Technique for SRAM Write Drivers [p. 1480]
Gourary, M.M.
Analysis of Oscillator Injection Locking by Harmonic Balance Method [p. 318]
Graeb, H.
Sizing Rules for Bipolar Analog Circuit Design [p. 140]
Grasset, A.
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Groeseneken, G.
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies [p. 1322]
Groβe, D.
Quantified Synthesis of Reversible Logic [p. 1015]
Grüttner, K.
SystemC-Based Modeling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder [p. 128]
Gu, X.
Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects [p. 252]
Guerin, X.
Efficient Implementation of Native Software Simulation for MPSoC [p. 676]
Guiducci, C.
Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces [p. 1328]
Guironnet de Massas, P.
Comparison of Memory Write Policies for NoC Based Multicore Cache Coherent Systems [p. 997]
Güleyüpoglu, E.
A Generic Standard Cell Design Methodology for Differential Circuit Styles [p. 843]
Gullapalli, K.K.
Analysis of Oscillator Injection Locking by Harmonic Balance Method [p. 318]
Gupta, A.
Completeness in SMT-Based BMC for Software Programs [p. 831]
Gupta, R.
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization [p. 110]
Gupta, S.
Multi-Vector Tests: A Path to Perfect Error-Rate Testing [p. 1178]
Gürkaynak, F.K.
A Generic Standard Cell Design Methodology for Differential Circuit Styles [p. 843]
Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces [p. 1328]
Guzmán-Miranda, H.
On the Design of Tunable Fault Tolerant Circuits on SRAM-Based FPGAs for Safety Critical Applications [p. 336]

H

Ha, S.
Architecture Exploration of NAND Flash-Based Multimedia Card [p. 218]
Habitz, P.A.
Optimal Margin Computation for At-Speed Test [p. 622]
Hahn, A.
Qalitative and Quantitative Analysis of IC Designs [p. 935]
Haid, J.
Impact of Leakage Current on Data Retention of RF-Powered Devices during Amplitude-Modulation-Based Communication [p. 784]
Halak, B.
Bandwidth-Centric Optimization for Area-Constrained Links with Crosstalk Avoidance Methods [p. 438]
Hamouche, R.
A Methodology for Improving Software Design Lifecycle in Embedded Control Systems [p. 533]
Han, Y.
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology [p. 891]
Hanselmann, H.
Model-Based Design Is Nice, But... [p. 555]
PANEL - The Future Car: Technology, Methods and Tools [p. 812]
Hanumolu, P.K.
Periodic Steady-State Analysis Augmented with Design Equality Constraints [p. 312]
Hartmann, J.
PANEL - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm [p. 510]
Hashemi, M.
Exact and Approximate Task Assignment Algorithms for Pipelined Software Synthesis [p. 746]
Hatami, S.
A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect [p. 568]
Haubelt, C.
Symbolic Reliability Analysis and Optimization of ECU Networks [p. 158]
Hauer, J.
Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement [p. 868]
Häusler, S.
Qalitative and Quantitative Analysis of IC Designs [p. 935]
Hausmann, K.
Qalitative and Quantitative Analysis of IC Designs [p. 935]
Haverkort, B.R.
Quantitative Evaluation in Embedded System Design: Predicting Battery Lifetime in Mobile Devices [p. 90]
Hedrich, L.
Model Checking of Analog Systems Using an Analog Specification Language [p. 324]
Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology [p. 800]
Heijligers, M.J.M.
Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors [p. 991]
Heinecke, H.
Software Components for Reliable Automotive Systems [p. 549]
Heineke, H.
PANEL - The Future Car: Technology, Methods and Tools [p. 812]
Hellwig, F.
System Performance Optimization Methodology for Infineon's 32-Bit Automotive Microcontroller Architecture [p. 962]
Henkel, J.
Run-Time System for an Extensible Embedded Processor with Dynamic Instruction Set [p. 752]
Instruction Re-Encoding Facilitating Dense Embedded Code [p. 770]
Minimizing Virtual Channel Buffer for Routers in On-Chip Communication Architectures [p. 1238]
Henriksson, T.
Video Processing Requirements on SoC Infrastructures [p. 1124]
Henzinger, T.A.
Logical Reliability of Interacting Real-Time Tasks [p. 909]
Hermanns, H.
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures [p. 88]
Herrería Garcia, J.A.
Safe Automatic Flight Back and Landing of Aircraft. Flight Reconfiguration Function (FRF) [p. 280]
Hersemeule, R.
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures [p. 88]
Hinn, W.
Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement [p. 868]
Hirech, M.
Test Strategies for Low Power Devices [p. 728]
Hölzenspies, P.K.F.
Run-Time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSoC) [p. 212]
Hoene, E.
A Novel Approach for EMI Design of Power Electronics [p. 170]
Hohenauer, M.
Retargetable Code Optimization for Predicated Execution [p. 1492]
Hollstein, T.
Multicast Parallel Pipeline Routing Architecture FOR Network-on-Chip [p. 1396]
Hong, S.
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution [p. 242]
Hong, S.-M.
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication [p. 1244]
Hooman, J.
Dependability for High-Tech Systems: An Industry-as-Laboratory Approach [p. 1226]
Hoover, G.
Synthesizing Synchronous Elastic Flow Networks [p. 306]
Hosseinabady, M.
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs [p. 1370]
Hsiao, M.S.
Efficient Design Validation Based on Cultural Algorithms [p. 402]
Simulation-Directed Invariant Mining for Software Verification [p. 682]
A Fast Approximation Algorithm for MIN-ONE SAT [p. 1087]
Hu, X.S.
Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs [p. 288]
Hu, Y.
iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing [p. 1184]
Huang, C.-Y.
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification [p. 813]
Huang, K.
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor [p. 792]
Huang, L.
Re-Examining the Use of Network-on-Chip as Test Access Mechanism [p. 808]
Hübner, M.
Cost - And Power Optimized FPGA Based System Integration: Methodologies and Integration of a Low-Power Capacity- Based Measurement Application on Xilinx FPGAs [p. 50]
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Hurink, J.L.
Run-Time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSoC) [p. 212]
Huss, S.
Specification and Design Considerations for Reliable Embedded Systems [p. 1111]
Hustin, S.
Industrial IP Integration Flows Based on IP-XACTTM Standards [p. 32]
Hwang, Y.
Cycle-approximate Retargetable Performance Estimation at the Transaction Level [p. 3]

I

Ienne, P.
Variable Latency Speculative Adder: A New Paradigm for Arithmetic Circuit Design [p. 1250]
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming [p. 1256]
Iercan, D.
Logical Reliability of Interacting Real-Time Tasks [p. 909]
Inaç, O.
A Generic Standard Cell Design Methodology for Differential Circuit Styles [p. 843]
Ishebabi, H.
High-Level Modeling and Exploration of Coarse-Grained Re-Configurable Architectures [p. 1334]
Israr, A.
Specification and Design Considerations for Reliable Embedded Systems [p. 1111]
Ito, N.
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network [p. 537]
Izosimov, V.
Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints [p. 915]
Synthesis of Fault-Tolerant Embedded Systems [p. 1117]

J

Jacquemod, G.
A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design [p. 804]
Jas, A.
A Low-Cost Concurrent Error Detection Technique for Processor Control Logic [p. 897]
Jerke, G.
On the Verification of High-Order Constraint Compliance in IC Design [p. 26]
Jiang, R.
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation [p. 580]
Jones, T.M.
Instruction Cache Energy Saving Through Compiler Way-Placement [p. 1196]
Joshi, S.
An Efficient FPGA Implementation of Principle Component Analysis Based Network Intrusion Detection System [p. 1160]
Josko, B.
Software Components for Reliable Automotive Systems [p. 549]
Jung, H.
Resilient Dynamic Power Management under Uncertainty [p. 224]

K

K, R.
Process Variation Aware Issue Queue Design [p. 1438]
Kacprowicz, R.
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs [p. 1103]
Kaczer, B.
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies [p. 1322]
Kahng, S.
MAGELLAN: A Search and Machine Learning-Based Framework for Fast Multi-Core Design Space Exploration and Optimization [p. 1432]
Kakoee, M.R.
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs [p. 1370]
Kalligeros, E.
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores [p. 474]
Kapralos, M.
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation [p. 1172]
Kapur, R.
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction [p. 462]
Katoen, J.-P.
Quantitative Evaluation in Embedded System Design: Trends in Modeling and Analysis Techniques [p. 86]
Kavousianos, X.
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores [p. 474]
Kazmierski, T. J.
Efficient Circuit-Level Modeling of Ballistic CNT Using Piecewise Non-Linear Approximation of Mobile Charge Density [p. 146]
Integrated Approach to Energy Harvester Mixed Technology Modeling and Performance Optimization [p. 704]
Keezer, D.C.
Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications [p. 1486]
Keitel-Schulz, D.
3D Integration or How to Scale in the 21st Century [p. 1516]
Kerckenaere, S.
Theoretical and Practical Aspects of IDDQ Settling - Impact on Measurement Timing and Quality [p. 1310]
Khaligh, R.S.
Accuracy-Adaptive Simulation of Transaction Level Models [p. 788]
Khatri, S.P.
A Delay-Efficient Radiation-Hard Digital Design Approach Using CWSP Elements [p. 354]
Energy Efficient and High Speed On-Chip Ternary Bus [p. 515]
A Single-supply True Voltage Level Shifter [p. 979]
Clock Distribution Scheme Using Coplanar Transmission Lines [p. 985]
Khoo, K.-Y.
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification [p. 813]
Kiefer, V.
PANEL - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm [p. 510]
Kim, M.
Constraint Refinement for Online Verifiable Cross-Layer System Adaptation [p. 646]
Kim, S.
Architecture Exploration of NAND Flash-Based Multimedia Card [p. 218]
Kim, T.
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution [p. 242]
Kirsch, C.M.
Logical Reliability of Interacting Real-Time Tasks [p. 909]
Kirsten, T.
Verification of Temporal Properties in Automotive Embedded Software [p. 164]
Kleanthous, M.
CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and Its Application to Instruction Caches [p. 1426]
Klimm, A.
A System Architecture for Reconfigurable Trusted Platforms [p. 541]
Klotz, T.
Automatic Generation of Complex Properties for Hardware Designs [p. 545]
Knaeblein, J.
Implementation of Parallel LFSR-Based Applications on an Adaptive DSP Featuring a Pipelined Configurable Gate Array [p. 1444]
Knobel, R.
Adaptive Simulation for Single-Electron Devices [p. 1021]
Ko, H.F.
On Automated Trigger Event Generation in Post-Silicon Validation [p. 256]
Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation [p. 1298]
Kocak, T.
Front End Device for Content Networking [p. 1456]
Koch, K.
An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs [p. 698]
Kocik, R.
A Methodology for Improving Software Design Lifecycle in Embedded Control Systems [p. 533]
Koenig, R.
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms [p. 604]
Kopetz, H.
Software Components for Reliable Automotive Systems [p. 549]
PANEL - The Future Car: Technology, Methods and Tools [p. 812]
Reliable Services in an Imperfect World [p. 1123]
Koushanfar, F.
EPIC: Ending Piracy of Integrated Circuits [p. 1069]
Kreutz, S.
Run-Time System for an Extensible Embedded Processor with Dynamic Instruction Set [p. 752]
Kropf, T.
Verification of Temporal Properties in Automotive Embedded Software [p. 164]
Kruijtzer, W.
Industrial IP Integration Flows Based on IP-XACTTM Standards [p. 32]
Kuchcinski, K.
Automatic Selection of Application-Specific Reconfigurable Processor Extensions [p. 1214]
Kuehnle, M.
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Kuenemund, T.
Impact of Leakage Current on Data Retention of RF-Powered Devices during Amplitude-Modulation-Based Communication [p. 784]
Kulikowski, K.J.
Power Balanced Gates Insensitive to Routing Capacitance Mismatch [p. 1280]
Kumar, A.
Vectorization of Reed Solomon Decoding and Mapping on the EVP [p. 450]
Kumar, R.
MAGELLAN: A Search and Machine Learning-Based Framework for Fast Multi-Core Design Space Exploration and Optimization [p. 1432]
Kundu, S.
On Modeling and Testing of Lithography Related Open Faults In Nano-CMOS Circuits [p. 616]
Kuper, J.
Run-Time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSoC) [p. 212]
Kuzmanov, G.
Merged Computation for Whirlpool Hashing [p. 272]
Memory Organization with Multi-Pattern Parallel Accesses [p. 1420]
Kwark, Y.H.
Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects [p. 252]
Kwon, W.-C.
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication [p. 1244]

L

Lai, C.-Y.
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification [p. 813]
Lajolo, M.
Variation Tolerant NoC Design by Means of Self-Calibrating Links [p. 1402]
Lamb, L.C.
Using UML as Front-End for Heterogeneous Software Code Generation Strategies [p. 504]
Lambrechts, A.
Scenario-Based Fixed-Point Data Format Refinement to Enable Energy-Scalable Software Defined Radios [p. 722]
Lange, P.
Hot Wire Anemometric MEMs Sensor for Water Flow Monitoring [p. 342]
Langen, D.
Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor [p. 276]
Langendoen, K.
Software for Wireless Networked Embedded Systems [p. 372]
Larsen, K.G.
A Game-Theoretic Approach to Real-Time System Testing [p. 486]
Larsson, A.
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns [p. 188]
Larsson, E.
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns [p. 188]
Laulanet, F.
Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment [p. 873]
Lauwereins, R.
PANEL - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm [p. 510]
Le, H.M.
Quantified Synthesis of Reversible Logic [p. 1015]
Le Guernic, P.
Compositional Design of Isochronous Systems [p. 928]
Leblebici, Y.
A Generic Standard Cell Design Methodology for Differential Circuit Styles [p. 843]
Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces [p. 1328]
Lee, J.
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation [p. 1172]
Leinweber, L.
Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction [p. 373]
Lekatsas, H.
Adaptive Filesystem Compression for Embedded Systems [p. 1374]
Lemonnier, F.
Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA [p. 610]
Leppelt, P.
Determining the Technical Complexity of Integrated Circuits [p. 935]
Lettnin, D.
Verification of Temporal Properties in Automotive Embedded Software [p. 164]
Leupers, R.
High-Level Modeling and Exploration of Coarse-Grained Re-Configurable Architectures [p. 1334]
Retargetable Code Optimization for Predicated Execution [p. 1492]
Leutgeb, T.
Impact of Leakage Current on Data Retention of RF-Powered Devices during Amplitude-Modulation-Based Communication [p. 784]
Lewicki, A.
A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design [p. 804]
Li, D.
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis [p. 432]
Li, J.
iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At- Speed Scan-Based Testing [p. 1184]
Li, M.
Optimizating Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures [p. 444]
Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications [p. 598]
Li, S.
A Game-Theoretic Approach to Real-Time System Testing [p. 486]
A Novel Technique for Improving Temperature Independency of Ring-ADC [p. 694]
Li, X.
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology [p. 891]
iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At- Speed Scan-Based Testing [p. 1184]
Li, Y.
CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns [p. 885]
Li, Z.
A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs [p. 740]
Lienig, J.
Novel Pin Assignment Algorithms for Components with Very High Pin Counts [p. 837]
Lilja, D.J.
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods [p. 348]
Limberg, T.
A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs [p. 780]
Lin, H.
Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency [p. 758]
Lin, Y.-T.
Physically-Aware N-Detect Test Pattern Selection [p. 634]
Lindgren, P.
TinyTimber, Reactive Objects in C for Real-Time Embedded Systems [p. 1382]
Lindsay, I.
Automated Dynamic Throughput-Constrained Structural-Level Pipelining in Streaming Applications [p. 1358]
Lissner, A.
A Novel Approach for EMI Design of Power Electronics [p. 170]
Liu, B.
Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression [p. 527]
Signal Probability Based Statistical Timing Analysis [p. 562]
Liu, S.
Energy Aware Dynamic Voltage and Frequency Selection for Real-Time Systems with Energy Harvesting [p. 236]
Liu, Y.-Y.
Wire Sizing Alternative - An Uniform Dual-Rail Routing Architecture [p. 796]
Locatelli, R.
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Loeckx, J.
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies [p. 1322]
Loeliger, T.
Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement [p. 868]
Loi, I.
Developing Mesochronous Synchronizers to Enable 3D NoCs [p. 1414]
Lombardi, F.
Error Detection/Correction in DNA Algorithmic Self-Assembly [p. 1079]
Lotfi-Kamran, P.
BARP- A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs [p. 1408]
Lu, Y.
An Efficient Algorithm for Free Resources Management on the FPGA [p. 1095]
Intelligent Merging OnLine Task Placement Algorithm for Partially Reconfigurable Systems [p. 1346]
Lublinerman, R.
Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams [p. 1504]
Lucas, C.
BARP- A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs [p. 1408]
Luk, W.
Using Reconfigurable Logic to Optimise GPU Memory Accesses [p. 44]
Lukasiewycz, M.
Symbolic Reliability Analysis and Optimization of ECU Networks [p. 158]

M

Maciel, P.
ezRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis [p. 1510]
Macii, A.
A Scalable Algorithmic Framework FOR Row-Based Power-Gating [p. 379]
Macii, E.
A Scalable Algorithmic Framework FOR Row-Based Power-Gating [p. 379]
Process Variation Tolerant Design Through a Placement-Aware Multiple Voltage Island Design Style [p. 967]
Optimal MTCMOS Reactivation under Power Supply Noise and Performance Constraints [p. 973]
Maillet-Contoz, L.
A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip [p. 9]
Makar, S.
CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns [p. 885]
Malani, P.
Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-Time Applications with Non-Deterministic Workload [p. 652]
Mallarapu, G.
A Single-supply True Voltage Level Shifter [p. 979]
Manhaeve, H.
Theoretical and Practical Aspects of IDDQ Settling - Impact on Measurement Timing and Quality [p. 1310]
Maraninchi, F.
A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip [p. 9]
Marconi, T.
An Efficient Algorithm for Free Resources Management on the FPGA [p. 1095]
Intelligent Merging OnLine Task Placement Algorithm for Partially Reconfigurable Systems [p. 1346]
Marculescu, R.
User-Aware Dynamic Resource Allocation in Networks-on-Chip [p. 1232]
Margull, U.
An Application-Based EDF Scheduler For OSEK/VDX [p. 1045]
Maricau, E.
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies [p. 1322]
Marinissen, E. J.
Analysis of the Test Data Volume Reduction Benefit of Modular SOC Testing [p. 182]
Markov, I.L.
Random Stimulus Generation Using Entropy and XOR Constraints [p. 664]
EPIC: Ending Piracy of Integrated Circuits [p. 1069]
Marques-Silva, J.
Algorithms for Maximum Satisfiability Using Unsatisfiable Cores [p. 408]
Martinez, A.P.
A Generic Standard Cell Design Methodology for Differential Circuit Styles [p. 843]
Martýn-Martýnez, J.
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies [p. 1322]
Maruccia, G.
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Masera, G.
VLSI Implementation of SISO Arithmethic Decoder FOR Joint Source Channel Coding [p. 1075]
Masrur, A.
Improvements in Polynomial-Time Feasibility Testing for EDF [p. 1033]
Massier, T.
Sizing Rules for Bipolar Analog Circuit Design [p. 140]
Mathew, J.
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs [p. 1370]
Mattes, H.
Optimal High-Resolution Spectral Analyzer [p. 62]
May, M.
A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder [p. 456]
Mayaram, K.
Periodic Steady-State Analysis Augmented with Design Equality Constraints [p. 312]
Mayer, A.
Industrial IP Integration Flows Based on IP-XACTTM Standards [p. 32]
System Performance Optimization Methodology for Infineon's 32-Bit Automotive Microcontroller Architecture [p. 962]
McGaughy, B.
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis [p. 432]
Medardoni, S.
Variation Tolerant NoC Design by Means of Self-Calibrating Links [p. 1402]
Meister, T.
Novel Pin Assignment Algorithms for Components with Very High Pin Counts [p. 837]
Melani, M.
Hot Wire Anemometric MEMs Sensor for Water Flow Monitoring [p. 342]
A Programmable and Low-EMI Integrated Half-Bridge Driver IN BCD Technology [p. 879]
Memik, G.
An Efficient FPGA Implementation of Principle Component Analysis Based Network Intrusion Detection System [p. 1160]
Mendelson, A.
Dependable Embeded Systems Day Panel: Issues and Challenges in Dependable Embedded Systems [p. 1394]
Merli, E.
Cooperative Safety: Combination Of Mutiple Technologies [p. 959]
Metzner, A.
Software Components for Reliable Automotive Systems [p. 549]
Meyerowitz, T.
Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor [p. 276]
Meyr, H.
High-Level Modeling and Exploration of Coarse-Grained Re-Configurable Architectures [p. 1334]
Retargetable Code Optimization for Predicated Execution [p. 1492]
Miller, D.M.
Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits [p. 1378]
Millet, P.
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Min, B.
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication [p. 1244]
Minier, D.
Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications [p. 1486]
Mir, S.
A General Method to Evaluate RF BIST Techniques Based on Non-Parametric Density Estimation [p. 68]
Mirimin, I.
Implementation of Parallel LFSR-Based Applications on an Adaptive DSP Featuring a Pipelined Configurable Gate Array [p. 1444]
Misra, S.
An Efficient FPGA Implementation of Principle Component Analysis Based Network Intrusion Detection System [p. 1160]
Mitra, S.
CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns [p. 885]
Globally Optimized Robust Systems to Overcome Scaled CMOS Challenges [p. 941]
Design Guidelines for Metallic-Carbon-Nanotube- Tolerant Digital Logic Circuits [p. 1009]
Dependable Embeded Systems Day Panel: Issues and Challenges in Dependable Embedded Systems [p. 1394]
Mödl, S.
Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement [p. 868]
Mohanram, K.
Approximate Logic Circuits for Low Overhead, Non-Intrusive Concurrent Error Detection [p. 903]
Mokhov, A.
Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis [p. 1142]
Molnos, A.M.
Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors [p. 991]
Momeni, M.
Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation [p. 688]
Monchiero, M.
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications [p. 1039]
Moon, U.-K.
Periodic Steady-State Analysis Augmented with Design Equality Constraints [p. 312]
Moonen, A.
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip [p. 300]
Morgado, A.
A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications [p. 862]
Moser, C.
An Efficient Solar Energy Harvester for Wireless Sensor Nodes [p. 104]
Robust and Low Complexity Rate Control for Solar Powered Sensors [p. 230]
Mucci, C.
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Implementation of Parallel LFSR-Based Applications on an Adaptive DSP Featuring a Pipelined Configurable Gate Array [p. 1444]
Müller, M.
Software Protection Mechanisms for Dependable Systems [p. 947]
Müller-Glaser, K.
A System Architecture for Reconfigurable Trusted Platforms [p. 541]
Muir, M.
Automated Dynamic Throughput-Constrained Structural-Level Pipelining in Streaming Applications [p. 1358]
Mukre, P.
Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-Time Applications with Non-Deterministic Workload [p. 652]
Mulas, F.
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures [p. 734]
Mulvaney, B.J.
Analysis of Oscillator Injection Locking by Harmonic Balance Method [p. 318]
Murali, S.
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization [p. 110]
Murgai R.
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network [p. 537]
Murgan, T.
An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs [p. 698]
Mutapcic, A.
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization [p. 110]
Mutyam, M.
Process Variation Aware Issue Queue Design [p. 1438]

N

Nadjm-Tehrani, S.
Tool Support for Incremental Failure Mode and Effects Analysis of Component-Based Systems [p. 921]
Nafrýa, M.
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies [p. 1322]
Nagpal, C.
A Delay-Efficient Radiation-Hard Digital Design Approach Using CWSP Elements [p. 354]
Nalla, P.K.
Verification of Temporal Properties in Automotive Embedded Software [p. 164]
Nani, C.
Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications [p. 1390]
Nanshi, K.
Improved Visibility in One-to-Many Trace Concretization [p. 819]
Narayan, S.
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation [p. 1172]
Navabi, Z.
BARP- A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs [p. 1408]
Ndai, P.
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking [p. 366]
Nebel, W.
On the Verification of High-Order Constraint Compliance in IC Design [p. 26]
SystemC-Based Modeling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder [p. 128]
Qalitative and Quantitative Analysis of IC Designs [p. 935]
Ness, D.C.
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods [p. 348]
Neumann, B.
Design Flow for Embedded FPGAs Based on a Flexible Architecture Template [p. 56]
Ney, A.
A Design-for-Diagnosis Technique for SRAM Write Drivers [p. 1480]
Ng, F.
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction [p. 462]
Nicolescu, G.
Semantics for Model-Based Validation of Continuous/Discrete Systems [p. 498]
Nicolici, N.
On Automated Trigger Event Generation in Post-Silicon Validation [p. 256]
Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation [p. 1298]
Nielsen, B.
A Game-Theoretic Approach to Real-Time System Testing [p. 486]
Noll, T. G.
Design Flow for Embedded FPGAs Based on a Flexible Architecture Template [p. 56]
Nordlander, J.
TinyTimber, Reactive Objects in C for Real-Time Embedded Systems [p. 1382]
Novo, D.
Optimizating Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures [p. 444]
Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications [p. 598]
A Coarse-Grained Array Based Baseband Processor for 100mbps+ Software Defined Radio [p. 716]
Scenario-Based Fixed-Point Data Format Refinement to Enable Energy-Scalable Software Defined Radios [p. 722]
Nurmi, J.
Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking [p. 264]
Nuzzo, P.
Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications [p. 1390]

O

O'Boyle, M.F.P.
Instruction Cache Energy Saving Through Compiler Way-Placement [p. 1196]
Ogg, S.
Serialized Asynchronous Links for NoC [p. 1003]
Oliveira, M.F.S.
Using UML as Front-End for Heterogeneous Software Code Generation Strategies [p. 504]
Oppenheimer, F.
SystemC-Based Modeling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder [p. 128]
Orailoglu, A.
Towards Fault Tolerant Parallel Prefix Adders in Nanoelectronic Systems [p. 360]
Ouy, J.
Compositional Design of Isochronous Systems [p. 928]
Ozer, S.
Efficient Symbolic Simulation of Low Level Software [p. 825]

P

Paek, Y.
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors [p. 1190]
Pakbaznia, E.
Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay-Budgeting [p. 385]
Palatin, P.
A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs [p. 740]
Palermo, G.
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications [p. 1039]
Pamunuwa, D.
Memory Technology for Extended Large-Scale Integration in Future Electronics Applications [p. 1126]
Pan, D.Z.
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices [p. 849]
Latch Modeling for Statistical Timing Analysis [p. 1136]
Panazzi, R.
Cooperative Safety: Combination Of Mutiple Technologies [p. 959]
Pandey, S.
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs [p. 206]
Paolieri, M.
An Adaptable FPGA-Based System for Regular Expression Matching [p. 1262]
Papachristou, C.
Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme [p. 1362]
Parameswaran, S.
A Formal Approach to the Protocol Converter Problem [p. 294]
Parandeh-Afshar, H.
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming [p. 1256]
Pardi, E.
A Programmable and Low-EMI Integrated Half-Bridge Driver IN BCD Technology [p. 879]
Park, C.
Architecture Exploration of NAND Flash-Based Multimedia Card [p. 218]
Park, S.
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors [p. 1190]
Paschalis, A.
Functional Self-Testing for Bus-Based Symmetric Multiprocessors
Paselli, M.
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks [p. 1027]
Patil, N.P.
Design Guidelines for Metallic-Carbon-Nanotube- Tolerant Digital Logic Circuits [p. 1009]
Patil, S.
A Low-Cost Concurrent Error Detection Technique for Processor Control Logic [p. 897]
Paul, S.
Harvesting Wasted Heat in a Microprocessor Using Thermo-Electric Generators: Modeling, Analysis And Measurement [p. 98]
Paulsson, K.
Cost - And Power Optimized FPGA Based System Integration: Methodologies and Integration of a Low-Power Capacity- Based Measurement Application on Xilinx FPGAs [p. 50]
Pecheux, F.
Modeling and Refining Heterogeneous Systems with SystemC-AMS: Application to WSN [p. 134]
Pedram, M.
Resilient Dynamic Power Management under Uncertainty [p. 224]
Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay-Budgeting [p. 385]
A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect [p. 568]
Penders, J.
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks
Peng, Z.
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns [p. 188]
A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems [p. 556]
Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints [p. 915]
Temperature-Aware Voltage Selection for Energy Optimization [p. 1083]
Synthesis of Fault-Tolerant Embedded Systems [p. 1117]
Pétrot, F.
Efficient Implementation of Native Software Simulation for MPSoC [p. 676]
Comparison of Memory Write Policies for NoC Based Multicore Cache Coherent Systems [p. 997]
Phillips, J.R.
Efficient Representation and Analysis of Power Grids [p. 420]
Pieralisi, L.
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Pileggi, L.
Automated Testability Enhancements for Logic Brick Libraries [p. 480]
Pineda De Gyvez, J.
Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters [p. 74]
Pinello, C.
Logical Reliability of Interacting Real-Time Tasks [p. 909]
Pittau, M.
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures [p. 734]
Planes, J.
Algorithms for Maximum Satisfiability Using Unsatisfiable Cores [p. 408]
Plaza, S.M.
Random Stimulus Generation Using Entropy and XOR Constraints [p. 664]
Poku, O.
Physically-Aware N-Detect Test Pattern Selection [p. 634]
Poledna, S.
Dependable Embeded Systems Day Panel: Issues and Challenges in Dependable Embedded Systems [p. 1394]
Polian, I.
Resistive Bridging Fault Simulation of Industrial Circuits [p. 628]
Pomeranz, I.
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy [p. 1166]
A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution [p. 1474]
Poncino, M.
A Scalable Algorithmic Framework FOR Row-Based Power-Gating [p. 379]
Pop, P.
Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints [p. 915]
Synthesis of Fault-Tolerant Embedded Systems [p. 1117]
Poppen, F.
Qalitative and Quantitative Analysis of IC Designs [p. 935]
Porrmann, M.
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography [p. 1462]
Pradhan, A.
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches [p. 523]
Pradhan, D.K.
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs [p. 1370]
Pravadelli, G.
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces [p. 396]
Pravossoudovitch, S.
A Design-for-Diagnosis Technique for SRAM Write Drivers [p. 1480]
Psarakia, M.
Functional Self-Testing for Bus-Based Symmetric Multiprocessors [p. 1304]
Pullini, A.
A Scalable Algorithmic Framework FOR Row-Based Power-Gating [p. 379]
Purnaprajna, M.
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography [p. 1462]
Puthenpurayil, S.
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications [p. 1220]
Puttmann, C.
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography [p. 1462]

Q

Qiu, M.
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints [p. 1202]
Qiu, Q.
A Framework of Stochastic Power Management Using Hidden Markov Model [p. 92]
Energy Aware Dynamic Voltage and Frequency Selection for Real-Time Systems with Energy Harvesting [p. 236]
Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-Time Applications with Non-Deterministic Workload [p. 652]
Qu, Y.
Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking [p. 264]

R

Rabou, S.
A Coarse-Grained Array Based Baseband Processor for 100mbps+ Software Defined Radio [p. 716]
Radetzki, M.
Accuracy-Adaptive Simulation of Transaction Level Models [p. 788]
Rafiliu, S.
A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems [p. 556]
Raghunathan, A.
Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor [p. 1148]
Ramalingam, A.
Latch Modeling for Statistical Timing Analysis [p. 1136]
Ramesh, S.
A Formal Approach to the Protocol Converter Problem [p. 294]
Rao, W.
Towards Fault Tolerant Parallel Prefix Adders in Nanoelectronic Systems [p. 360]
Ravikumar, C.P.
Test Strategies for Low Power Devices [p. 728]
Real, D.
Defeating Classical Hardware Countermeasures: A New Processing for Side Channel Analysis [p. 1274]
Recas, J.
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks [p. 1027]
Rech Wagner, F.
Dynamic Task Allocation Strategies in MPSoC for Soft Real-Time Applications [p. 1386]
Redaelli, F.
Task Scheduling with Configuration Prefetching and Anti-Fragmentation Techniques on Dynamically Reconfigurable Systems [p. 519]
Reddy, S.M.
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy [p. 1166]
A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution [p. 1474]
Redin, R.
Using UML as Front-End for Heterogeneous Software Code Generation Strategies [p. 504]
Reimann, F.
Symbolic Reliability Analysis and Optimization of ECU Networks [p. 158]
Reitemeyer, S.
Verification of Temporal Properties in Automotive Embedded Software [p. 164]
Reyneri, L.
PWM-Based Test Stimuli Generation for BIST of High Resolution Sigma-Delta ADCS [p. 284]
Ricotti, G.
A Programmable and Low-EMI Integrated Half-Bridge Driver IN BCD Technology [p. 879]
Ries, F.
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Rimolo-Donadio, R.
Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects [p. 252]
Rincón, F.J.
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks [p. 1027]
Ristau, B.
A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs [p. 780]
Ritter, M.B.
Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects [p. 252]
Rodrýguez R.
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies [p. 1322]
Rogin, F.
Automatic Generation of Complex Properties for Hardware Designs [p. 545]
Rosenstiel, W.
Verification of Temporal Properties in Automotive Embedded Software [p. 164]
Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits [p. 937]
Rox, J.
Modeling Event Stream Hierarchies with Hierarchical Event Models [p. 492]
Roy, J.A.
EPIC: Ending Piracy of Integrated Circuits [p. 1069]
Roy, K.
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking [p. 366]
Ruch, O.
Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA [p. 610]
Rueda, A.
Practical Implementation of a Network Analyzer for Analog BIST Applications [p. 80]
Rülke, S.
Automatic Generation of Complex Properties for Hardware Designs [p. 545]
Ruf, J.
Verification of Temporal Properties in Automotive Embedded Software [p. 164]
Rusakov, S.G.
Analysis of Oscillator Injection Locking by Harmonic Balance Method [p. 318]
Rutenbar, R.A.
Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing [p. 856]
Rutzig, M.B.
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications [p. 1208]

S

Sabatini, M.
Physical Architectures of Automotive Systems [p. 391]
Safari, S.
Scalable Architecture for On-Chip Neural Network Training Using Swarm Intelligence [p. 1340]
Saha, S.
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications [p. 1220]
Sakiyama, K.
FPGA Design for Algebraic Tori Based Public Key Cryptography [p. 1292]
Samii, S.
A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems [p. 556]
Samman, F.A.
Multicast Parallel Pipeline Routing Architecture FOR Network-on-Chip [p. 1396]
Sánchez Eles, M.
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks [p. 1027]
Sander, O.
A System Architecture for Reconfigurable Trusted Platforms [p. 541]
Sangiovanni-Vincentelli, A.
Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor [p. 276]
Physical Architectures of Automotive Systems [p. 391]
Software Components for Reliable Automotive Systems [p. 549]
Methods, Tools and Standards for the Analysis and Evaluation of Modern Automotive Architectures [p. 659]
Logical Reliability of Interacting Real-Time Tasks [p. 909]
Santambrogio, M.D.
Task Scheduling with Configuration Prefetching and Anti-Fragmentation Techniques on Dynamically Reconfigurable Systems [p. 519]
An Adaptable FPGA-Based System for Regular Expression Matching [p. 1262]
Sanyal, A.
On Modeling and Testing of Lithography Related Open Faults In Nano-CMOS Circuits [p. 616]
Saponara, S.
Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications [p. 1390]
Sarlotte, M.
Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components [p. 330]
Sarmiento, R.
GMDS: Hardware Inplementation of Novel Real Output Queuing Architecture [p. 1450]
Sathanur, A.
A Scalable Algorithmic Framework FOR Row-Based Power-Gating [p. 379]
Sattler, S.
Optimal High-Resolution Spectral Analyzer [p. 62]
Sauermann, M.
Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor [p. 276]
Sazeides, Y.
CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and Its Application to Instruction Caches [p. 1426]
Schat, J.
Fault Clustering in Deep-Submicron CMOS Processes [p. 511]
Scheer, P.
CARbridge, Reduction of System Complexity by Standardization of the System-Basis-Chips for Automotive Applications [p. 1107]
Schirner, G.
Introducing Preemptive Scheduling in Abstract RTOS Models Using Result Oriented Modeling [p. 122]
Schlessman, J.
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications [p. 1220]
Schlichtmann, U.
Sizing Rules for Bipolar Analog Circuit Design [p. 140]
Schloeffe, J.
Resistive Bridging Fault Simulation of Industrial Circuits [p. 628]
Schmid, A.
Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces [p. 1328]
Schmidt, E.
CARbridge, Reduction of System Complexity by Standardization of the System-Basis-Chips for Automotive Applications [p. 1107]
Schneider, A.
Implementation of Parallel LFSR-Based Applications on an Adaptive DSP Featuring a Pipelined Configurable Gate Array [p. 1444]
Schnepp, J.
Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM Devices [p. 776]
Schönknecht, V.
Verification of Temporal Properties in Automotive Embedded Software [p. 164]
Schramm, A.
Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM Devices [p. 776]
Schroeder, B.
A Novel Approach for EMI Design of Power Electronics [p. 170]
Schuster, C.
Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects [p. 252]
Sciuto, D.
Task Scheduling with Configuration Prefetching and Anti-Fragmentation Techniques on Dynamically Reconfigurable Systems [p. 519]
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications [p. 1039]
Scuderi, A.
Cooperative Safety: Combination Of Mutiple Technologies [p. 959]
Sha, E.H.-M.
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints [p. 1202]
Shafique, M.
Run-Time System for an Extensible Embedded Processor with Dynamic Instruction Set [p. 752]
Shahidi, S.
Multi-Vector Tests: A Path to Perfect Error-Rate Testing [p. 1178]
Shalev, J.
Efficient Symbolic Simulation of Low Level Software [p. 825]
Shang, L.
Adaptive Simulation for Single-Electron Devices [p. 1021]
Shann, J.-J.
Instruction Set Extension Exploration in Multiple-Issue Architecture [p. 764]
Shao, Z.
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints [p. 1202]
Shi, R.
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network [p. 537]
Shi, S.X.
Latch Modeling for Statistical Timing Analysis [p. 1136]
Shi, X.
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices [p. 849]
Shibuya, T.
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network [p. 537]
Shrivastava, A.
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors [p. 1190]
Silva, J.M.S.
Efficient Representation and Analysis of Power Grids [p. 420]
Silveira, L.M.
Efficient Representation and Analysis of Power Grids [p. 420]
SPARE - A Scalable Algorithm for Passive, Structure Preserving, Parameter-Aware Model Order Reduction [p. 586]
Sinanoglu, O.
Analysis of the Test Data Volume Reduction Benefit of Modular SOC Testing [p. 182]
Singerman, E.
Efficient Symbolic Simulation of Low Level Software [p. 825]
Singh, B.
Retargetable Code Optimization for Predicated Execution [p. 1492]
Singhal, S.
Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing [p. 856]
Singhee, A.
Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing [p. 856]
Siti, M.
Cooperative Safety: Combination Of Mutiple Technologies [p. 959]
Slomka, F.
An Application-Based EDF Scheduler For OSEK/VDX [p. 1045]
Smit, G.J.M.
Run-Time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSoC) [p. 212]
Computation of Buffer Capacities for Throughput Constrained and Data Dependent Inter-Task Communication [p. 640]
Soininen, J.-P.
Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking [p. 264]
Somenzi, F.
Improved Visibility in One-to-Many Trace Concretization [p. 819]
Sonza Reorda, M.
A Novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers [p. 194]
Sorel, Y.
A Methodology for Improving Software Design Lifecycle in Embedded Control Systems [p. 533]
Sousa, L.
Merged Computation for Whirlpool Hashing [p. 272]
Sowmya, A.
A Formal Approach to the Protocol Converter Problem [p. 294]
Sreedhar, A.
On Modeling and Testing of Lithography Related Open Faults In Nano-CMOS Circuits [p. 616]
Srivastava, N.
High-Frequency Mutual Impedance Extraction of VLSI Interconnects in the Presence of a Multi-Layer Conducting Substrate [p. 426]
Stechele, W.
Hardware/Software Architecture of an Algorithm for Vision-Based Real-Time Vehicle Detection in Dark Environments [p. 176]
Stehr, M.-O.
Constraint Refinement for Online Verifiable Cross-Layer System Adaptation [p. 646]
Steinhorst, S.
Model Checking of Analog Systems Using an Analog Specification Language [p. 324]
Sterpone, L.
On the Design of Tunable Fault Tolerant Circuits on SRAM-Based FPGAs for Safety Critical Applications [p. 336]
Straka, B.
Theoretical and Practical Aspects of IDDQ Settling - Impact on Measurement Timing and Quality [p. 1310]
Stratigopoulos, H.-G.
A General Method to Evaluate RF BIST Techniques Based on Non-Parametric Density Estimation [p. 68]
Strik, M.
Subsystem Exchange in a Concurrent Design Process Environment [p. 953]
Stripf, T.
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms [p. 604]
Stube, B.
A Novel Approach for EMI Design of Power Electronics [p. 170]
Stuijk, S.
Parametric Throughput Analysis of Synchronous Data Flow Graphs [p. 116]
Stuyt, J.
Industrial IP Integration Flows Based on IP-XACTTM Standards [p. 32]
Suaya, R.
High-Frequency Mutual Impedance Extraction of VLSI Interconnects in the Presence of a Multi-Layer Conducting Substrate [p. 426]
Sun, G.
A Variation Aware High Level Synthesis Framework [p. 1063]
Sundareswaran, S.
Transistor-Specific Delay Modeling for SSTA [p. 592]

T

Talayssat, J.
A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design [p. 804]
Talcott, C.
Constraint Refinement for Online Verifiable Cross-Layer System Adaptation [p. 646]
Talpin, J.-P.
Compositional Design of Isochronous Systems [p. 928]
Tan, S.X.-D.
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis [p. 432]
Tan, Y.
A Framework of Stochastic Power Management Using Hidden Markov Model [p. 92]
Tang, S.
In-Band Cross-Trigger Event Transmission for Transaction-Based Debug [p. 414]
Tang, Y.
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor [p. 792]
Tardieu, O.
Programming Shared Memory Multiprocessors with Deterministic Message-Passing Concurrency: Compiling SHIM to Pthreads [p. 1498]
Taubin, A.
Power Balanced Gates Insensitive to Routing Capacitance Mismatch [p. 1280]
Taylor, B.
Automated Testability Enhancements for Logic Brick Libraries [p. 480]
Tchegho, A.
Optimal High-Resolution Spectral Analyzer [p. 62]
Tehranipoor, M.
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation [p. 1172]
Teich, J.
Symbolic Reliability Analysis and Optimization of ECU Networks [p. 158]
Temam, O.
A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs [p. 740]
Tenentes, V.
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores [p. 474]
Tenhunen, H.
On Analysis and Synthesis of (n,k)-Non-Linear Feedback Shift Registers [p. 1286]
Teslenko, M.
On Analysis and Synthesis of (n,k)-Non-Linear Feedback Shift Registers [p. 1286]
Thiele, L.
An Efficient Solar Energy Harvester for Wireless Sensor Nodes [p. 104]
Robust and Low Complexity Rate Control for Solar Powered Sensors [p. 230]
Thoguluva, J.
Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor [p. 1148]
Thomke, G.
Novel Pin Assignment Algorithms for Components with Very High Pin Counts [p. 837]
Thonnart, Y.
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures [p. 88]
Thornton, M.A.
Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits [p. 1378]
Tobajas, F.
GMDS: Hardware Inplementation of Novel Real Output Queuing Architecture [p. 1450]
Tombs, J.
On the Design of Tunable Fault Tolerant Circuits on SRAM-Based FPGAs for Safety Critical Applications [p. 336]
Tongbong, J.
A General Method to Evaluate RF BIST Techniques Based on Non-Parametric Density Estimation [p. 68]
Torah, R.N.
Integrated Approach to Energy Harvester Mixed Technology Modeling and Performance Optimization [p. 704]
Torres, A.
Transistor-Specific Delay Modeling for SSTA [p. 592]
Tracy Weed, J.
PANEL - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm [p. 510]
Tripakis, S.
Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams [p. 1504]
Tumeo, A.
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications [p. 1039]

U

Ulyanov, S.L.
Analysis of Oscillator Injection Locking by Harmonic Balance Method [p. 318]

V

Valette, F.
Defeating Classical Hardware Countermeasures: A New Processing for Side Channel Analysis [p. 1274]
Valli, E.
Serialized Asynchronous Links for NoC [p. 1003]
Van Berkel, K.
Performance Analysis of SoC Architectures Based on Latency-Rate Servers [p. 200]
Vectorization of Reed Solomon Decoding and Mapping on the EVP [p. 450]
van den Berg, R.
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip [p. 300]
Van der Perre, L.
Optimizating Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures [p. 444]
Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications [p. 598]
A Coarse-Grained Array Based Baseband Processor for 100mbps+ Software Defined Radio [p. 716]
Scenario-Based Fixed-Point Data Format Refinement to Enable Energy-Scalable Software Defined Radios [p. 722]
Van der Plas, G.
Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications [p. 1390]
van der Wolf, P.
Industrial IP Integration Flows Based on IP-XACTTM Standards [p. 32]
Performance Analysis of SoC Architectures Based on Latency-Rate Servers [p. 200]
Video Processing Requirements on SoC Infrastructures [p. 1124]
van Meerbergen, J.
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip [p. 300]
Vanzolini, L.
Implementation of Parallel LFSR-Based Applications on an Adaptive DSP Featuring a Pipelined Configurable Gate Array [p. 1444]
Vasilevski, M.
Modeling and Refining Heterogeneous Systems with SystemC-AMS: Application to WSN [p. 134]
Vassiliadis, S.
Merged Computation for Whirlpool Hashing [p. 272]
Vasudevan, N.
Programming Shared Memory Multiprocessors with Deterministic Message-Passing Concurrency: Compiling SHIM to Pthreads [p. 1498]
Vaumorin, E.
Industrial IP Integration Flows Based on IP-XACTTM Standards [p. 32]
Vázquez, D.
Practical Implementation of a Network Analyzer for Analog BIST Applications [p. 80]
Velev, M.N.
Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems [p. 1268]
Vemu, R.
A Low-Cost Concurrent Error Detection Technique for Processor Control Logic [p. 897]
Vemuri, R.
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches [p. 523]
Venkatarama, V.
Power Balanced Gates Insensitive to Routing Capacitance Mismatch [p. 1280]
Venkatasubramanian, N.
Constraint Refinement for Online Verifiable Cross-Layer System Adaptation [p. 646]
Verbauwhede, I.
FPGA Design for Algebraic Tori Based Public Key Cryptography [p. 1292]
Verdier, F.
Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components [p. 330]
Verma, A.K.
Variable Latency Speculative Adder: A New Paradigm for Arithmetic Circuit Design [p. 1250]
Vernay, D.
Perspective on Embedded Systems: Challenges, Solutions and Research Priorities [p.2]
Versen, M.
Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM Devices [p. 776]
Vietti, P.
A Generic Standard Cell Design Methodology for Differential Circuit Styles [p. 843]
Vincis, F.
A Programmable and Low-EMI Integrated Half-Bridge Driver IN BCD Technology [p. 879]
Vink, J. P.
Performance Analysis of SoC Architectures Based on Latency-Rate Servers [p. 200]
Virazel, A.
A Design-for-Diagnosis Technique for SRAM Write Drivers [p. 1480]
Visweswariah, C.
Optimal Margin Computation for At-Speed Test [p. 622]
Incremental Criticality and Yield Gradients [p. 1130]
Vitkovski, A.
Design of A HW/SW Communication Infrastructure for A Heterogeneous Reconfigurable Processor [p. 1352]
Memory Organization with Multi-Pattern Parallel Accesses [p. 1420]
Vöolker, M.
Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement [p. 868]
Vogt, T.
A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment [p. 38]
Von Sydow, T.
Design Flow for Embedded FPGAs Based on a Flexible Architecture Template [p. 56]
Vörg, A.
Quantitative Productivity Measurement in IC Design [p. 934]
Vrudhula, S.
Current Source Based Standard Cell Model for Accurate Signal Integrity and Timing Analysis [p. 574]
Vytyaz, I.
Periodic Steady-State Analysis Augmented with Design Equality Constraints [p. 312]

W

Wagner, F.
Using UML as Front-End for Heterogeneous Software Code Generation Strategies [p. 504]
Wagner, I.
MCjammer: Adaptive Verification for Multi-Core Designs [p. 670]
Walker, R.A.
Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems [p. 260]
Wang, D.
Latch Modeling for Statistical Timing Analysis [p. 1136]
Wang, F.
A Variation Aware High Level Synthesis Framework [p. 1063]
Wang, J.
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor [p. 792]
Wang, L.
Integrated Approach to Energy Harvester Mixed Technology Modeling and Performance Optimization [p. 704]
Wang, X.
Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology [p. 800]
Wang, Z.
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation [p. 580]
Power Balanced Gates Insensitive to Routing Capacitance Mismatch [p. 1280]
Wappler, U.
Software Protection Mechanisms for Dependable Systems [p. 947]
Weber, T.
PANEL - The Future Car: Technology, Methods and Tools [p. 812]
Wehn, N.
A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment [p. 38]
A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder [p. 456]
Weinberger, K.
Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits [p. 937]
Wen, X.
Test Strategies for Low Power Devices [p. 728]
Wenzel Brião, E.
Dynamic Task Allocation Strategies in MPSoC for Soft Real-Time Applications [p. 1386]
Wiggers, M.H.
Computation of Buffer Capacities for Throughput Constrained and Data Dependent Inter-Task Communication [p. 640]
Wilcock, R.
A New Approach for Combining Yield and Performance in Behavioral Models for Analogue Integrated Circuits [p. 152]
Wilhelm, R.
Methods, Tools and Standards for the Analysis and Evaluation of Modern Automotive Architectures [p. 659]
Wille, R.
Quantified Synthesis of Reversible Logic [p. 1015]
Williams, P.
Subsystem Exchange in a Concurrent Design Process Environment [p. 953]
Wilson, P.
A New Approach for Combining Yield and Performance in Behavioral Models for Analogue Integrated Circuits [p. 152]
Wirrer, G.
An Application-Based EDF Scheduler For OSEK/VDX [p. 1045]
Wolf, W.
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications [p. 1220]
Wolff, F.
Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme [p. 1362]
Wolinski, C.
Automatic Selection of Application-Specific Reconfigurable Processor Extensions [p. 1214]
Wu, I.-W.
Instruction Set Extension Exploration in Multiple-Issue Architecture [p. 764]
Wu, Q.
Energy Aware Dynamic Voltage and Frequency Selection for Real-Time Systems with Energy Harvesting [p. 236]
Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-Time Applications with Non-Deterministic Workload [p. 652]
Wu, W.
Efficient Design Validation Based on Cultural Algorithms [p. 402]
Wunderlich, H.-J.
Scan Chain Organization for Embedded Diagnosis [p. 468]

X

Xie, Y.
A Variation Aware High Level Synthesis Framework [p. 1063]
Xiong, J.
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation [p. 580]
Optimal Margin Computation for At-Speed Test [p. 622]
Incremental Criticality and Yield Gradients [p. 1130]
Xu, J.
Simultaneous FU and Register Binding Based on Network Flow Method [p. 1057]
Xu, Q.
In-Band Cross-Trigger Event Transmission for Transaction-Based Debug [p. 414]
Re-Examining the Use of Network-on-Chip as Test Access Mechanism [p. 808]
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology [p. 891]
iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At- Speed Scan-Based Testing [p. 1184]
Xue, C.J.
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints [p. 1202]

Y

Yakovlev, A.
Bandwidth-Centric Optimization for Area-Constrained Links with Crosstalk Avoidance Methods [p. 438]
Serialized Asynchronous Links for NoC [p. 1003]
Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis [p. 1142]
Yoneda, T.
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects [p. 1366]
Yoo, S.
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution [p. 242]
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication [p. 1244]
Yoshida, H.
Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits [p. 1099]
Young, J.
Capturing and Analyzing IC Design Productivity Metrics [p. 936]
Yu, W.
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network [p. 537]
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation [p. 580]
Yu, Z.
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation [p. 580]
Yuan, F.
Re-Examining the Use of Network-on-Chip as Test Access Mechanism [p. 808]

Z

Zambreno, J.
An Efficient FPGA Implementation of Principle Component Analysis Based Network Intrusion Detection System [p. 1160]
Zeng, H.
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor [p. 792]
Zeng, J.-K.
Deep Submicro Interconnect Timing Model with Quadratic Random Variable Analysis [p. 1091]
Zezza, S.
VLSI Implementation of SISO Arithmethic Decoder FOR Joint Source Channel Coding [p. 1075]
Zhang, G.
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor [p. 792]
Zhang, J.
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits [p. 1009]
Zhang, L.
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network [p. 537]
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology [p. 891]
Zhang, W.
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network [p. 537]
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation [p. 580]
Zhao, Q.
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks [p. 1027]
Zharov, M.M.
Analysis of Oscillator Injection Locking by Harmonic Balance Method [p. 318]
Zhong, L.
Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-Based Integration [p. 268]
Zhou, D.
Efficient Circuit-Level Modeling of Ballistic CNT Using Piecewise Non-Linear Approximation of Mobile Charge Density [p. 146]
Zhou, F.
A Novel Technique for Improving Temperature Independency of Ring-ADC [p. 694]
Zhou, Y.
Harvesting Wasted Heat in a Microprocessor Using Thermo-Electric Generators: Modeling, Analysis And Measurement [p. 98]
Zhu, Y.
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network [p. 537]
Zhu, Z.
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network [p. 537]
Zidouni, M.
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures [p. 88]
Zilic, Z.
Built-In Clock Skew System for On-Line Debug and Repair [p. 248]
Zimek, B.
Impact of Leakage Current on Data Retention of RF-Powered Devices during Amplitude-Modulation-Based Communication [p. 784]
Zjajo, A.
Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters [p. 74]
Zolotov, V.
Optimal Margin Computation for At-Speed Test [p. 622]
Zolotov, V.
Incremental Criticality and Yield Gradients [p. 1130]