DATE 2006 AUTHOR INDEX

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

A

Abbas, M.
On-Chip 8GHz Non-Periodic High-Swing Noise Detector [p. 670]
Abbaspour, S.
Non-Gaussian Statistical Interconnect Timing Analysis [p. 533]
Abdollahi, A.
Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams [p. 317]
Abraham, J. A.
Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessors [p. 496]
Acquaviva, A.
Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study [p. 15]
A Control Theoretic Approach to Run-Time Energy Optimization of Pipelined Processing in MPSoCs [p. 876]
Ademaj, A.
A Time-Triggered Ethernet (TTE) Switch [p. 794]
Ahmed, W.
Faster Exploration of High Level Design Alternatives Using UML for Better Partitions [p. 579]
Ahn, M.
A Spatial Mapping Algorithm for Heterogeneous Coarse-Grained Reconfigurable Architectures [p. 363]
Aitken, R.
Low-Power Design Tools: Are EDA Vendors Taking this Matter Seriously? [p. 1227]
Akgul, B. E. S.
Ultra Efficient (Embedded) SoC Architectures Based on Probabilistic CMOS (PCMOS) Technology [p. 1110]
Alam, M. A.
Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits [p. 780]
Al-Ars, Z.
Space of DRAM Fault Models and Corresponding Testing [p. 1252]
Albrecht, C.
A Dynamically Reconfigurable Packet-Switched Network-on-Chip [p. 136]
Efficient Incremental Clock Latency Scheduling for Large Circuits [p. 1091]
Al-Hashimi, B. M.
Minimizing Test Power in SRAM through Reduction of Pre-Charge Activity [p. 1159]
Alimonda, A.
A Control Theoretic Approach to Run-Time Energy Optimization of Pipelined Processing in MPSoCs [p. 876]
Al-Junaid, H.
HDL Models of Ferromagnetic Core Hysteresis Using Timeless Discretisation of the Magnetic Slope [p. 644]
Alkadi, G.
A Unified System-Level Modeling and Simulation Environment for MPSoC Design: MPEG-4 Decoder Case Study [p. 474]
Almukhaizim, S.
Berger Code-Based Concurrent Error Detection in Asynchronous Burst-Mode Machines [p. 71]
Ameliard, B.
Reducing the Sub-Threshold and Gate-Tunneling Leakage of SRAM Cells Using Dual-Vt and Dual-Tox Assignment [p. 995]
Angiolini, F.
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness [p. 124]
An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration [p. 1145]
Anis, M.
An Analytical State Dependent Leakage Power Model for FPGAs [p. 612]
Arm, C.
The Ultra Low-Power WiseNET System [p. 971]
Arpinen, T.
Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications [p. 1324]
Arslan, H.
Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFs and Localized Slack-Satisfaction Computations [p. 768]
Arslan, T.
System-Level Scheduling on Instruction Cell Based Reconfigurable Systems [p. 381]
Asada, K.
On-Chip 8GHz Non-Periodic High-Swing Noise Detector [p. 670]
Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization [p. 884]
Asadi, H.
Vulnerability Analysis of L2 Cache Elements to Single Event Upsets [p. 1276]
Asai, H.
Large Scale RLC Circuit Analysis Using RLCG-MNA Formulation [p. 45]
Ascheid, G.
A SW Performance Estimation Framework for Early System-Level-Design Using Fine-Grained Instrumentation [p. 468]
Automatic ADL-Based Operand Isolation for Embedded Processors [p. 600]
An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support [p. 919]
Askar, S.
Efficient Factorization of DSP Transforms Using Taylor Expansion Diagram [p. 754]
Atienza, D.
Dynamic Data Type Refinement Methodology for Systematic Performance-Energy Design Exploration of Network Applications [p. 740]
Automated Exploration of Pareto-Optimal Configurations in Parameterized Dynamic Memory Allocation for Embedded Systems [p. 874]

B

Babighian, P.
Enabling Fine-Grain Leakage Management by Voltage Anchor Insertion [p. 868]
Baghdadi, A.
ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding [p. 1330]
Bahar, R. I.
Designing MRF Based Error Correcting Circuits for Memory Elements [p. 792]
Balachandran, J.
Analysis and Modeling of Power Grid Transmission Lines [p. 33]
Balakrishnan, K. J.
Efficient Unknown Blocking Using LFSR Reseeding [p. 1051]
Balarin, F.
Communication and Co-Simulation Infrastructure for Heterogeneous System Integration [p. 462]
Functional Verification Methodology Based on Formal Interface Specification and Transactor Generation [p. 1013]
Ballapuram, C.
Microarchitectural Floorplanning under Performance and Thermal Tradeoff [p. 1288]
Banaiyan, A.
A Concurrent Testing Method for NoC Switches [p. 1171]
Bancel, F.
A Secure Scan Design Methodology [p. 1177]
Banerjee, N.
Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating [p. 862]
Banerjee, P.
Smart Bit-Width Allocation for Low Power Optimization in a SystemC Based ASIC Design Environment [p. 618]
Bansal, A.
Circuit-Aware Device Design Methodology for Nanometer Technologies: A Case Study for Low Power SRAM Design [p. 983
Bartzas, A.
Dynamic Data Type Refinement Methodology for Systematic Performance-Energy Design Exploration of Network Applications [p. 740]
Barua, R.
An Integrated Scratch-Pad Allocator for Affine and Non-Affine Code [p. 925]
Baschirotto, A.
A Synthesis Tool for Power-Efficient Base-Band Filter Design [p. 162]
Basu, A.
Battery-Aware Code Partitioning for a Text to Speech System [p. 672]
Basu, P.
What Lies between Design Intent Coverage and Model Checking? [p. 1217]
Bautista, T.
A Unified System-Level Modeling and Simulation Environment for MPSoC Design: MPEG-4 Decoder Case Study [p. 474]
Becker, L. B.
Optimizing the Generation of Object-Oriented Real-Time Embedded Applications Based on the Real-Time Specification for Java [p. 806]
Beltrame, G.
Exploiting TLM and Object Introspection for System-Level Simulation [p. 100]
Ben Hassen, J.
On the Numerical Verification of Probabilistic Rewriting Systems [p. 1223]
Benini, L.
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness [p. 124]
Combining Simulation and Formal Methods for System-Level Performance Analysis [p. 236]
Application Specific NoC Design [p. 491]
Exploring "Temperature-Aware" Design in Low-Power MPSoCs [p. 838]
Enabling Fine-Grain Leakage Management by Voltage Anchor Insertion [p. 868]
An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration [p. 1145]
Benny, O.
Distributed Object Models for Multi-Processor SoC's, with Application to Low-Power Multimedia Wireless Systems [p. 482]
Benso, A.
Automatic March Tests Generations for Static Linked Faults in SRAMs [p. 1258]
Bensoudane, E.
Distributed Object Models for Multi-Processor SoC's, with Application to Low-Power Multimedia Wireless Systems [p. 482]
Bergamaschi, R.A.
Heterogeneous Behavioral Hierarchy for System Level Designs [p. 565]
Bernardi, P.
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis In SoCs [p. 412]
Bernasconi, A.
Efficient Minimization of Fully Testable 2-SPP Networks [p. 1300]
Bertacco, V.
Distance-Guided Hybrid Verification with GUIDO [p. 1211]
Bertels, K.
Compiler-Driven FPGA-Area Allocation for Reconfigurable Computing [p. 369]
Bertozzi, D.
Communication-Aware Allocation and Scheduling Framework for Stream-Oriented Multi-Processor Systems-on-Chip [p. 3]
Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study [p. 15]
Bertozzi, S.
Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study [p. 15]
Beutel, J.
Fast-prototyping Using the BTnode Platform [p. 977]
Beyne, E.
Analysis and Modeling of Power Grid Transmission Lines [p. 33]
Bhaduri, D.
A Hybrid Framework for Design and Analysis of Fault-Tolerant Architectures for Nanoscale Molecular Crossbar Memories [p. 335]
Bhanja, S.
Novel Designs for Thermally Robust Coplanar Crossing in QCA [p. 786]
Bhunia, S.
Ultralow Power Computing with Sub-Threshold Leakage: A Comparative Study of Bulk and SOI Technologies [p. 856]
Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating [p. 862]
Bickford, J.
DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations and Increased Defect Sensitivity in Digital, Analogue and Mixed-Signal Circuit Design [p. 387]
Biswas, P.
Automatic Identification of Application-Specific Functional Units with Architecturally Visible Storage [p. 212]
Blaauw, D.
An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits [p. 164]
Blanton, R. D.
Extraction of Defect Density and Size Distributions from Wafer Sort Test Results [p. 913]
Boelcskei, H.
Advanced Receiver Algorithms for MIMO Wireless Communication [p. 593]
Bojnordi, M. N.
A Concurrent Testing Method for NoC Switches [p. 1171]
Bolotin, E.
Efficient Link Capacity and QoS Design for Network-on-Chip [p. 9]
Bombieri, N.
On the Evaluation of Transactor-Based Verification for Reusing TLM Assertions and Testbenches at RTL [p. 1007]
Bonivento, A.
Platform-Based Design of Wireless Sensor Networks for Industrial Applications[p. 1103]
Bonnet, P.
Hogthrob: Towards a Sensor Network Infrastructure for Sow Monitoring [p. 1109]
Borgmann, M.
Advanced Receiver Algorithms for MIMO Wireless Communication [p. 593]
Borrione, D.
Proven Correct Monitors from PSL Specifications [p. 1246]
Bosio, A.
Automatic March Tests Generations for Static Linked Faults in SRAMs [p. 1258]
Bouganis, C.-S.
Hardware Efficient Architectures for Eigenvalue Computation [p. 953]
Bounceur, A.
Pseudorandom Functional BIST for Linear and Nonlinear MEMS [p. 664]
Boutillon, E.
Efficient Factorization of DSP Transforms Using Taylor Expansion Diagram [p. 754]
Brack, T.
Disclosing the LDPC Code Decoder Design Space [p. 200]
Brandão do Nascimento, P. S.
Temporal Partitioning for Image Processing Based on Time-Space Complexity in Reconfigurable Architectures [p. 375]
Braun, M.
Virtual Prototyping of Embedded Platforms for Wireless and Multimedia [p. 488]
Brebels, S.
Analysis and Modeling of Power Grid Transmission Lines [p. 33]
Brebner, G.
Memory Centric Thread Synchronization on Platform FPGAs [p. 959]
Brewer, F.
Layout Driven Data Communication Optimization for High Level Synthesis [p. 1185]
Bringmann, O.
Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design [p. 242]
Brisk, P.
Layout Driven Data Communication Optimization for High Level Synthesis [p. 1185]
Bronckers, S.
Systematic Stability-Analysis Method for Analog Circuits [p. 150]
Brown, J. G.
Extraction of Defect Density and Size Distributions from Wafer Sort Test Results [p. 913]
Budnik, M.
Minimizing Ohmic Loss and Supply Voltage Variation Using a Novel Distributed Power Supply Network [p. 1116]
Buehler, M.
DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations and Increased Defect Sensitivity in Digital, Analogue and Mixed-Signal Circuit Design [p. 387]
Buergin, F.
Two-Phase Resonant Clocking for Ultra-Low-Power Hearing Aid Applications [p. 73]
Burg, A.
Advanced Receiver Algorithms for MIMO Wireless Communication [p. 593]

C

Cadambi, S.
Power Analysis of Mobile 3D Graphics [p. 502]
Cai, W.
Time Domain Model Order Reduction by Wavelet Collocation Method [p. 21]
Carbognani, F.
Two-Phase Resonant Clocking for Ultra-Low-Power Hearing Aid Applications [p. 73]
Carchon, G.
Analysis and Modeling of Power Grid Transmission Lines [p. 33]
Carloni, L. P.
Platform-Based Design of Wireless Sensor Networks for Industrial Applications[p. 1103]
Carro, L.
An RF Improved Loopback for Test Time Reduction [p. 646]
Carta, S.
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness [p. 124]
A Control Theoretic Approach to Run-Time Energy Optimization of Pipelined Processing in MPSoCs [p. 876]
Caseiro, R.
The Ultra Low-Power WiseNET System [p. 971]
Catthoor, F.
Distributed Loop Controller Architecture for Multi-Threading in Uni-Threaded VLIW Processors [p. 339]
Dynamic Data Type Refinement Methodology for Systematic Performance-Energy Design Exploration of Network Applications [p. 740]
Automated Exploration of Pareto-Optimal Configurations in Parameterized Dynamic Memory Allocation for Embedded Systems [p. 874]
Scalable Performance-Energy Trade-Off Exploration of Embedded Real-Time Systems on Multiprocessor Platforms [p. 1073]
Cazeaux, J. M.
Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects [p. 170]
Ceng, J.
An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration [p. 1145]
Chai, D.
Building a Better Boolean Matcher and Symmetry Detector [p. 1079]
Chakrabarti, P. P.
What Lies between Design Intent Coverage and Model Checking? [p. 1217]
Chakrabarty, K.
Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips [p. 285]
Droplet Routing in the Synthesis of Digital Microfluidic Biochips [p. 323]
Test Set Enrichment Using a Probabilistic Fault Model and the Theory of Output Deviations [p. 1270]
Chakraborty, A.
Thermal Resilient Bounded-Skew Clock Tree Optimization Methodology [p. 832]
Chakradhar, S. T.
Efficient Unknown Blocking Using LFSR Reseeding [p. 1051]
Coverage Loss by Using Space Compactors in Presence of Unknown Values [p. 1053]
Chakrapani, L. N.
Ultra Efficient (Embedded) SoC Architectures Based on Probabilistic CMOS (PCMOS) Technology [p. 1110]
Chang, D.-M.
A Built-In Redundancy-Analysis Scheme for RAMS with 2D Redundancy Using 1D Local Bitmap [p. 53]
Chang, N.
Communication Architecture Optimization: Making the Shortest Path Shorter in Regular Networks-on-Chip [p. 712]
Chang, Y.-J.
An Ultra Low-Power TLB Design [p. 1122]
Chao, M. C.-T.
Coverage Loss by Using Space Compactors in Presence of Unknown Values [p. 1053]
Charbon, E.
A Single Photon Avalanche Diode Array Fabricated in Deep-Submicron CMOS Technology [p. 81]
Chatha, K. S.
A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures [p. 130]
Chatterjee, A.
Online RF Checkers for Diagnosing Multi-Gigahertz Automatic Test Boards on Low Cost ATE Platforms [p. 658]
Chattopadhyay, A.
Automatic ADL-Based Operand Isolation for Embedded Processors [p. 600]
Cheemalavagu, S.
Ultra Efficient (Embedded) SoC Architectures Based on Probabilistic CMOS (PCMOS) Technology [p. 1110]
Chen, C.C-P.
Statistical Timing Analysis with Path Reconvergence and Spatial Correlations [p. 528]
G. Chen
Activity Clustering for Leakage Management in SPMs [p. 696]
Dynamic Scratch-Pad Memory Management for Irregular Array Access Patterns [p. 931]
Chen, H.
Performance Optimization for Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems [p. 678]
Chen, J.-J.
Multiprocessor Synthesis for Periodic Hard Real-Time Tasks under a Given Energy Constraint [p. 1061]
Chen, K.C.
Energy Efficiency vs. Programmability Trade-off: Architectures and Design Principles [p. 587]
Chen, Q.
Circuit-Aware Device Design Methodology for Nanometer Technologies: A Case Study for Low Power SRAM Design [p. 983
Chen, T.
Modeling Multiple Input Switching of CMOS Gates in DSM Technology Using HDMR [p. 626]
Chen, X.
Communication and Co-Simulation Infrastructure for Heterogeneous System Integration [p. 462]
Cheng, H.
Online Energy-Aware I/O Device Scheduling for Hard Real-Time Systems [p. 1055]
Cheng, K.-.T
Timing-Reasoning-Based Delay Fault Diagnosis [p. 418]
Multiple-Fault Diagnosis Based on Single-Fault Activation and Single-Output Observation [p. 424]
Coverage Loss by Using Space Compactors in Presence of Unknown Values [p. 1053]
Cherroun, H.
Scheduling under Resource Constraints Using Dis-Equations [p. 1067]
Cheung, P. Y. K.
Hardware Efficient Architectures for Eigenvalue Computation [p. 953]
Chiang, C.
Time Domain Model Order Reduction by Wavelet Collocation Method [p. 21]
Chiarulli, D. M.
Nonlinear Model Order Reduction Using Remainder Functions [p. 281]
Cho, H.
Lock-Free Synchronization for Dynamic Embedded Real-Time Systems [p. 438]
Cho, N.
A Network-On-Chip with 3gbps/Wire Serialized On-Chip Interconnect Using Adaptive Control Schemes [p. 79]
Choi, J. H.
Dynamic Bit-Width Adaptation in DCT : Image Quality Versus Computation Energy Trade-Off [p. 520]
Choi, K.
A Spatial Mapping Algorithm for Heterogeneous Coarse-Grained Reconfigurable Architectures [p. 363]
Choi, K.-M.
A Systematic IP and Bus Subsystem Modeling for Platform-Based System Design [p. 560]
Chopra, K.
An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits [p. 164]
Choudhury, M.
Battery-Aware Code Partitioning for a Text to Speech System [p. 672]
Cidon, I.
Efficient Link Capacity and QoS Design for Network-on-Chip [p. 9]
Ciesielski, M.
Efficient Factorization of DSP Transforms Using Taylor Expansion Diagram [p. 754]
Ciriani, V.
Efficient Minimization of Fully Testable 2-SPP Networks [p. 1300]
Coenen, M.
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips [p. 118]
Coker, D.
A Hybrid Framework for Design and Analysis of Fault-Tolerant Architectures for Nanoscale Molecular Crossbar Memories [p. 335]
Come, B.
A Synthesis Tool for Power-Efficient Base-Band Filter Design [p. 162]
Conrad, M.
Model-Based Development of In-Vehicle Software [p. 89]
Cornea, R.
Software Annotations for Power Optimization on Mobile Devices [p. 684]
Cotofana, S. D.
Compositional, Efficient Caches for a Chip Multi-Processor [p. 345]
Craninckx, J.
A Synthesis Tool for Power-Efficient Base-Band Filter Design [p. 162]
Cserveny, S.
The Ultra Low-Power WiseNET System [p. 971]
Culler, D.
Deploying Networks Based on TinyOS

D

D'Amico, S.
A Synthesis Tool for Power-Efficient Base-Band Filter Design [p. 162]
Darte, A.
Scheduling under Resource Constraints Using Dis-Equations [p. 1067]
Das, S.
What Lies between Design Intent Coverage and Model Checking? [p. 1217]
Dasgupta, P.
What Lies between Design Intent Coverage and Model Checking? [p. 1217]
De Bernardinis, F.
A Synthesis Tool for Power-Efficient Base-Band Filter Design [p. 162]
Bosschere, K. De
Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors [p. 351]
de Lima, M. E.
Temporal Partitioning for Image Processing Based on Time-Space Complexity in Reconfigurable Architectures [p. 375]
De Micheli, G.
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips [p. 118]
De Raedt, W.
Analysis and Modeling of Power Grid Transmission Lines [p. 33]
Decotignie, J.-D.
The Ultra Low-Power WiseNET System [p. 971]
Dégardins, P.
Electric and Electronic Vehicle Architecture Assessment [p. 558]
Dehaene, W.
From UML/SysML to Matlab/Simulink: Current State and Future Perspectives [p. 93]
Densmore, D.
FPGA Architecture Characterization for System Level Performance Analysis [p. 734]
D'Errico, J.
Constructing Portable Compiled Instruction-Set Simulators -- An ADL-Driven Approach [p. 112]
Desineni, R.
Extraction of Defect Density and Size Distributions from Wafer Sort Test Results [p. 913]
de Vries, R. Penning
EDA Challenges in the Converging Application World [p. 1]
Dey, S.
Integrated Data Relocation and Bus Reconfiguration for Adaptive System-on-Chip Platforms [p. 728]
Dhayni, A.
Pseudorandom Functional BIST for Linear and Nonlinear MEMS [p. 664]
Di Carlo, S.
Automatic March Tests Generations for Static Linked Faults in SRAMs [p. 1258]
Di Natale, G.
Automatic March Tests Generations for Static Linked Faults in SRAMs [p. 1258]
Dick, R.P.
Adaptive Chip-Package Thermal Analysis for Synthesis and Design [p. 844]
Dilillo, L.
Minimizing Test Power in SRAM through Reduction of Pre-Charge Activity [p. 1159]
Dimond, R.
Automating Processor Customisation: Optimised Memory Access and Resource Sharing [p. 206]
Carmo Lucas, A. do
A Reconfigurable HW/SW Platform for Computation Intensive High-Resolution Real-Time Digital Film Applications [p. 194]
Doboli, A.
ALAMO: An Improved Sigma-Space Based Methodology for Modeling Process Parameter Variations in Analog Circuits [p. 156]
Systematic Methodology for Designing Reconfigurable ΔΣ Modulator Topologies for Multimode Communication Systems [p. 393]
Dobrovolny, P.
Systematic Stability-Analysis Method for Analog Circuits [p. 150]
Doemer, R.
Quantitative Analysis of Transaction Level Models for the AMBA Bus [p. 230]
Doerr, H.
Model-Based Development of In-Vehicle Software [p. 89]
Domic, A.
Low-Power Design Tools: Are EDA Vendors Taking this Matter Seriously? [p. 1227]
Donlin, A.
FPGA Architecture Characterization for System Level Performance Analysis [p. 734]
Dorsch, R.
(145)Task-Accurate Performance Modeling in SystemC for Real-Time Multi-Processor Architectures [p. 480]
Drechsler, R.
On the Relation between Simulation-Based and SAT-Based Diagnosis [p. 1139]
Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks [p. 1225]
Efficient Minimization of Fully Testable 2-SPP Networks [p. 1300]
Duraisami, K.
Thermal Resilient Bounded-Skew Clock Tree Optimization Methodology [p. 832]
Dutt, N.
Automatic Identification of Application-Specific Functional Units with Architecturally Visible Storage [p. 212]
Software Annotations for Power Optimization on Mobile Devices [p. 684]
COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC [p. 700]
Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors [p. 1197]
Dutt, S.
Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFs and Localized Slack-Satisfaction Computations [p. 768]
Efficient On-Line Interconnect Testing in FPGAs with Provable Detectability for Multiple Faults [p. 1165]

E

Earlie, E.
Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors [p. 1197]
Edwards, S. A.
Optimizing Sequential Cycles through Shannon Decomposition and Retiming [p. 1085]
Eeckhout, L.
Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors [p. 351]
Eichner, S.
A Reconfigurable HW/SW Platform for Computation Intensive High-Resolution Real-Time Digital Film Applications [p. 194]
Ekpanyapong, M.
Microarchitectural Floorplanning under Performance and Thermal Tradeoff [p. 1288]
Eles, P.
Power Constrained and Defect-Probability Driven SoC Test Scheduling with Test Set Partitioning [p. 291]
Synthesis of Fault-Tolerant Schedules with Transparency/Performance Trade-Offs for Distributed Embedded Systems [p. 706]
Buffer Space Optimisation with Communication Synthesis and Traffic Shaping for NoCs [p. 718]
Formal Verification of SystemC Designs Using a Petri-Net Based Representation [p. 1228]
El-Hoyidi, A.
The Ultra Low-Power WiseNET System [p. 971]
Elmasry, M. I.
A 10 GHz 15 dB Four-Stage Distributed Amplifier in 0.18 μm CMOS Process [p. 405]
Enescu, F.
Equivalence Verification of Arithmetic Datapaths with Multiple Word-Length Operands [p. 824]
Enz, C.
The Ultra Low-Power WiseNET System [p. 971]
Eo, S.-K.
A Systematic IP and Bus Subsystem Modeling for Platform-Based System Design [p. 560]
Ernst, R.
A Reconfigurable HW/SW Platform for Computation Intensive High-Resolution Real-Time Digital Film Applications [p. 194]
Improved Offset-Analysis Using Multiple Timing-References [p. 450]
Eyerman, S.
Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors [p. 351]

F

Fach, R.
A Reconfigurable HW/SW Platform for Computation Intensive High-Resolution Real-Time Digital Film Applications [p. 194]
Falk, J.
(145)Task-Accurate Performance Modeling in SystemC for Real-Time Multi-Processor Architectures [p. 480]
Fallah, F.
Reducing the Sub-Threshold and Gate-Tunneling Leakage of SRAM Cells Using Dual-Vt and Dual-Tox Assignment [p. 995]
Optimizing High Speed Arithmetic Circuits Using Three-Term Extraction [p. 1294]
Fang, S. C.
Cooptimization of Interface Hardware and Software for I/O Controllers [p. 724]
Farine, P.-A.
Architectural and Technology Influence on the Optimal Total Power Consumption [p. 989]
Fatemi, H.
Non-Gaussian Statistical Interconnect Timing Analysis [p. 533]
Feautrier, P.
Scheduling under Resource Constraints Using Dis-Equations [p. 1067]
Felber, N.
Two-Phase Resonant Clocking for Ultra-Low-Power Hearing Aid Applications [p. 73]
Feng, L.
Time Domain Model Order Reduction by Wavelet Collocation Method [p. 21]
Ferrari, F.
An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration [p. 1145]
Ferri, C.
An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration [p. 1145]
Fettweis, G.
Energy Efficiency vs. Programmability Trade-off: Architectures and Design Principles [p. 587]
4G Applications, Architectures, Design Methodology and Tools for MPSoC [p. 830]
Fey, G.
On the Relation between Simulation-Based and SAT-Based Diagnosis [p. 1139]
Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks [p. 1225]
Fichtner, W.
Two-Phase Resonant Clocking for Ultra-Low-Power Hearing Aid Applications [p. 73]
Flottes, M.-L.
A Secure Scan Design Methodology [p. 1177]
Frehse, G.
Verifying Analog Oscillator Circuits Using Forward/Backward Abstraction Refinement [p. 257]
Friebel, D.
Low-Power Design Tools: Are EDA Vendors Taking this Matter Seriously? [p. 1227]
Friedman, J.
MATLAB/Simulink for Automotive Systems Design [p. 87]
Fuchs, S.
Test and Reliability Challenges in Automotive Microelectronics [p. 547]
Fujiwara, H.
Power-Constrained Test Scheduling for Multi-Clock Domain SoCs [p. 297]
Functional Constraints vs. Test Compression in Scan-Based Delay Testing. [p. 1039]
Fummi, F.
On the Evaluation of Transactor-Based Verification for Reusing TLM Assertions and Testbenches at RTL [p. 1007]

G

Gaedke, H.
TRAIN: A Virtual Transaction Layer Architecture for TLM-Based HW/SW Codesign of Synthesizable MPSoC [p. 1318]
Gallie, K.
Diagnosis of Defects on Scan Enable and Clock Trees [p. 436]
Gandhi, K. R.
Exploiting Data-Dependent Slack Using Dynamic Multi-VDD to Minimize Energy Consumption in Datapath Circuits [p. 1001]
Garcia, J.
Bootstrapped Full-Swing CMOS Driver for Low Supply Voltage Operation
Gebel, K.
A Reconfigurable HW/SW Platform for Computation Intensive High-Resolution Real-Time Digital Film Applications [p. 194]
Geukes, B.
Automatic ADL-Based Operand Isolation for Embedded Processors [p. 600]
Ghiasi, S.
Power-Aware Compilation for Embedded Processors with Dynamic Voltage Scaling and Adaptive Body Biasing Capabilities [p. 943]
Giannini, V.
A Synthesis Tool for Power-Efficient Base-Band Filter Design [p. 162]
Gielen, G.
Double-Strength CAFFEINE: Fast Template-Free Symbolic Modeling of Analog Circuits via Implicit Canonical Form Functions and Explicit Introns [p. 269]
Top-Down Heterogeneous Synthesis of Analog and Mixed-Signal Systems [p. 275]
Gill, B.
Soft Delay Error Analysis in Logic Circuits [p. 47]
Ginosar, R.
Efficient Link Capacity and QoS Design for Network-on-Chip [p. 9]
Girard, P.
Minimizing Test Power in SRAM through Reduction of Pre-Charge Activity [p. 1159]
Giroud, F.
The Ultra Low-Power WiseNET System [p. 971]
Giunchiglia, E.
Quantifier Structure in Search Based Procedures for QBFs [p. 812]
Gizopoulos, D.
Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications [p. 65]
Glesner, M.
A Signal Theory Based Approach to the Statistical Analysis of Combinatorial Nanoelectronic Circuits [p. 632]
Goddard, S.
Online Energy-Aware I/O Device Scheduling for Hard Real-Time Systems [p. 1055]
Goehner, P.
Test and Reliability Challenges in Automotive Microelectronics [p. 547]
Goel, S. K.
Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips [p. 285]
Goessel, M.
Test Set Enrichment Using a Probabilistic Fault Model and the Theory of Output Deviations [p. 1270]
Gokhale, M.
A Hybrid Framework for Design and Analysis of Fault-Tolerant Architectures for Nanoscale Molecular Crossbar Memories [p. 335]
Gomez-Prado, D.
Efficient Factorization of DSP Transforms Using Taylor Expansion Diagram [p. 754]
Gong, W.
Layout Driven Data Communication Optimization for High Level Synthesis [p. 1185]
Goossens, K.
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips [p. 118]
Graham, P.
A Hybrid Framework for Design and Analysis of Fault-Tolerant Architectures for Nanoscale Molecular Crossbar Memories [p. 335]
Greiner, A.
An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles [p. 94]
Grillinger, P.
A Time-Triggered Ethernet (TTE) Switch [p. 794]
Grosse, D.
Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks [p. 1225]
Groszschaedl, J.
Combining Algorithm Exploration with Instruction Set Design: A Case Study in Elliptic Curve Cryptography [p. 218]
Gu, Z.
Adaptive Chip-Package Thermal Analysis for Synthesis and Design [p. 844]
Guenzel, R.
TRAIN: A Virtual Transaction Layer Architecture for TLM-Based HW/SW Codesign of Synthesizable MPSoC [p. 1318]
Guerri, A.
Communication-Aware Allocation and Scheduling Framework for Stream-Oriented Multi-Processor Systems-on-Chip [p. 3]
Guillot, J.
Efficient Factorization of DSP Transforms Using Taylor Expansion Diagram [p. 754]
Guo, H.
Customization of Application Specific Heterogeneous Multi-Pipeline Processors [p. 746]
Gupta, A.
Disjunctive Image Computation for Embedded Software Verification [p. 1205]
Gupta, P.
Test Generation for Combinational Quantum Cellular Automata (QCA) Circuits [p. 311]
Gupta, R.
Parallel Co-Simulation Using Virtual Synchronization with Redundant Host Execution [p. 1151]
Guz, Z.
Efficient Link Capacity and QoS Design for Network-on-Chip [p. 9]
Gyger, S.
The Ultra Low-Power WiseNET System [p. 971]

H

Ha, S.
Dynamic Code Overlay of SDF-Modeled Programs on Low-End Embedded Systems [p. 945]
Parallel Co-Simulation Using Virtual Synchronization with Redundant Host Execution [p. 1151]
Habibi, A.
Efficient Assertion Based Verification Using TLM [p. 106]
Halatsis, C.
Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications [p. 65]
Hämäläinen, T. D.
Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications [p. 1324]
Hamdioui, S.
Space of DRAM Fault Models and Corresponding Testing [p. 1252]
Han, H.
Restructuring Field Layouts for Embedded Memory System [p. 937]
Handziski, V.
An Environment for Controlled Experiments with In-House Sensor Networks [p. 1108]
Hännikäinen, M.
Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications [p. 1324]
Hao, X.
Layout Driven Data Communication Optimization for High Level Synthesis [p. 1185]
Harbich, K.
Test and Reliability Challenges in Automotive Microelectronics [p. 547]
Harris, I. G.
A Coverage Metric for the Validation of Interacting Processes [p. 1019]
Haubelt, C.
(145)Task-Accurate Performance Modeling in SystemC for Real-Time Multi-Processor Architectures [p. 480]
Havinga, P. J. M.
Wireless Sensor Networks and Beyond [p. 970]
He, C.
RAS-NANO: A Reliability-Aware Synthesis Framework for Reconfigurable Nanofabrics [p. 1179]
He, Z.
Power Constrained and Defect-Probability Driven SoC Test Scheduling with Test Set Partitioning [p. 291]
Hély, D.
A Secure Scan Design Methodology [p. 1177]
Healy, M.
Microarchitectural Floorplanning under Performance and Thermal Tradeoff [p. 1288]
Heighton, J.
Designing Signal Processing Systems for FPGAs [p. 92]
Heijligers, M. J. M.
Compositional, Efficient Caches for a Chip Multi-Processor [p. 345]
Heiligers, M.
On Test Conditions for the Detection of Open Defects [p. 896]
Heinkel, U.
New Methods and Coverage Metrics for Functional Verification [p. 1025]
Heithecker, S.
A Reconfigurable HW/SW Platform for Computation Intensive High-Resolution Real-Time Digital Film Applications [p. 194]
Henia, R.
Improved Offset-Analysis Using Multiple Timing-References [p. 450]
Herkersdorf, A.
Performance Evaluation for System-on-Chip Architectures Using Trace-Based Transaction Level Simulation [p. 248]
AutoVision - Flexible Processor Architecture for Video-assisted Driving [p. 556]
Hermida, R.
Pre-Synthesis Optimization of Multiplications to Improve Circuit Performance [p. 1306]
Hibbeler, J.
DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations and Increased Defect Sensitivity in Digital, Analogue and Mixed-Signal Circuit Design [p. 387]
Hohenauer, M.
An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support [p. 919]
Hong, S.
A Systematic IP and Bus Subsystem Modeling for Platform-Based System Design [p. 560]
Hosangadi, A.
Optimizing High Speed Arithmetic Circuits Using Three-Term Extraction [p. 1294]
Hosseinabady, M.
A Concurrent Testing Method for NoC Switches [p. 1171]
Hsieh, H.
Communication and Co-Simulation Infrastructure for Heterogeneous System Integration [p. 462]
Hsu, H.-.R
Multiprocessor Synthesis for Periodic Hard Real-Time Tasks under a Given Energy Constraint [p. 1061]
Hu, J.
Integrated Placement and Skew Optimization for Rotary Clocking [p. 756]
Associative Skew Clock Routing for Difficult Instances [p. 762]
Hu, Y.
Statistical Timing Analysis with Path Reconvergence and Spatial Correlations [p. 528]
Huang, J.
Defect Tolerance of QCA Tiles [p. 774]
Huang, P.-K.
Power-Aware Compilation for Embedded Processors with Dynamic Voltage Scaling and Adaptive Body Biasing Capabilities [p. 943]
Huang, S. H.
Cooptimization of Interface Hardware and Software for I/O Controllers [p. 724]
Huang, Y.
Diagnosis of Defects on Scan Enable and Clock Trees [p. 436]
Hunt Jr., W. A.
Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessors [p. 496]
Huther, W.
A Reconfigurable HW/SW Platform for Computation Intensive High-Resolution Real-Time Digital Film Applications [p. 194]
Hwang, T. T.
Crosstalk-Aware Domino Logic Synthesis [p. 1312]
Hwang, W.
Droplet Routing in the Synthesis of Digital Microfluidic Biochips [p. 323]

I

Ienne, P.
Automatic Identification of Application-Specific Functional Units with Architecturally Visible Storage [p. 212]
Combining Algorithm Exploration with Instruction Set Design: A Case Study in Elliptic Curve Cryptography [p. 218]
Ignat, N.
Soft-Error Classification and Impact Analysis on Real-Time Operating Systems [p. 182]
Iizuka, T.
Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization [p. 884]
Ikeda, M.
On-Chip 8GHz Non-Periodic High-Swing Noise Detector [p. 670]
Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization [p. 884]
Irick, K.
Priority Scheduling in Digital Microfluidics-Based Biochips [p. 329]
Irwin, M. J.
Priority Scheduling in Digital Microfluidics-Based Biochips [p. 329]
Activity Clustering for Leakage Management in SPMs [p. 696]
On-Chip Bus Thermal Analysis and Optimization [p. 850]
Ishebabi, H.
Automatic ADL-Based Operand Isolation for Embedded Processors [p. 600]
Ito, H.
Concurrent Core Test for SoC Using Shared Test Set and Scan Chain Disable [p. 1045]
Ivancic, F.
Disjunctive Image Computation for Embedded Software Verification [p. 1205]
Iyengar, V.
Test Scheduling with Thermal Optimization for Network-on-Chip Systems Using Variable-Rate On-Chip Clocking [p. 652]
Izosimov, V.
Synthesis of Fault-Tolerant Schedules with Transparency/Performance Trade-Offs for Distributed Embedded Systems [p. 706]

J

Jacobi, C.
Evaluating Coverage of Error Detection Logic for Soft Errors Using Formal Methods [p. 176]
Jacome, M. F.
RAS-NANO: A Reliability-Aware Synthesis Framework for Reconfigurable Nanofabrics [p. 1179]
Jayapala, M.
Distributed Loop Controller Architecture for Multi-Threading in Uni-Threaded VLIW Processors [p. 339]
Jensen, E. D.
Lock-Free Synchronization for Dynamic Embedded Real-Time Systems [p. 438]
Jerinic, V.
New Methods and Coverage Metrics for Functional Verification [p. 1025]
Jézéquel, M.
ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding [p. 1330]
Jha, N. K.
Test Generation for Combinational Quantum Cellular Automata (QCA) Circuits [p. 311]
Jin, H. S.
Strong Conflict Analysis for Propositional Satisfiability [p. 818]
Jung, C.
Test and Reliability Challenges in Automotive Microelectronics [p. 547]

K

Kaeli, D.
Vulnerability Analysis of L2 Cache Elements to Single Event Upsets [p. 1276]
Kaeslin, H.
Two-Phase Resonant Clocking for Ultra-Low-Power Hearing Aid Applications [p. 73]
Kahng, A. B.
Lens Aberration Aware Timing-Driven Placement [p. 890]
Kalla, P
Equivalence Verification of Arithmetic Datapaths with Multiple Word-Length Operands [p. 824]
Kalligeros, E.
Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding [p. 1033]
Kammler, D.
Automatic ADL-Based Operand Isolation for Embedded Processors [p. 600]
Kanajan, S.
Exploring Trade-offs between Centralized versus Decentralized Automotive Architectures Using a Virtual Integration Environment [p. 548]
Kandemir, M.
Dynamic Partitioning of Processing and Memory Resources in Embedded MPSoC Architectures [p. 690]
Activity Clustering for Leakage Management in SPMs [p. 696]
Dynamic Scratch-Pad Memory Management for Irregular Array Access Patterns [p. 931]
Kane, R.
Monolithic Verification of Deep Pipelines with Collapsed Flushing [p. 1234]
Kang, K.
Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits [p. 780]
Kaplan, A.
Layout Driven Data Communication Optimization for High Level Synthesis [p. 1185]
Kar, S.
High Level Synthesis of Higher Order Continuous Time State Variable Filters with Minimum Sensitivity and Hardware Count [p. 1203]
Karakoy, M.
Dynamic Scratch-Pad Memory Management for Irregular Array Access Patterns [p. 931]
Karlsson, D.
Formal Verification of SystemC Designs Using a Petri-Net Based Representation [p. 1228]
Karuri, K.
A SW Performance Estimation Framework for Early System-Level-Design Using Fine-Grained Instrumentation [p. 468]
A Design Flow for Configurable Embedded Processors Based on Optimized Instruction Set Extension Synthesis [p. 581]
Kastner, R.
Layout Driven Data Communication Optimization for High Level Synthesis [p. 1185]
Optimizing High Speed Arithmetic Circuits Using Three-Term Extraction [p. 1294]
Kavousianos, X.
Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding [p. 1033]
Kazmierski, T.
HDL Models of Ferromagnetic Core Hysteresis Using Timeless Discretisation of the Magnetic Slope [p. 644]
Kempf, T.
A SW Performance Estimation Framework for Early System-Level-Design Using Fine-Grained Instrumentation [p. 468]
Khatri, S. P.
Bus Stuttering: An Encoding Technique to Reduce Inductive Noise in Off-Chip Data Transmission [p. 522]
Khawam, S.
System-Level Scheduling on Instruction Cell Based Reconfigurable Systems [p. 381]
Kiemb, M.
A Spatial Mapping Algorithm for Heterogeneous Coarse-Grained Reconfigurable Architectures [p. 363]
Kienle, F.
Disclosing the LDPC Code Decoder Design Space [p. 200]
Kim, D.
Parallel Co-Simulation Using Virtual Synchronization with Redundant Host Execution [p. 1151]
Kim, H.
A Network-On-Chip with 3gbps/Wire Serialized On-Chip Interconnect Using Adaptive Control Schemes [p. 79]
Kim, J.
Restructuring Field Layouts for Embedded Memory System [p. 937]
Kim, K.
A Network-On-Chip with 3gbps/Wire Serialized On-Chip Interconnect Using Adaptive Control Schemes [p. 79]
Kim, M.-S.
Associative Skew Clock Routing for Difficult Instances [p. 762]
Kim, S.
Restructuring Field Layouts for Embedded Memory System [p. 937]
Area-Efficient Error Protection for Caches [p. 1282]
Kim, T.
A Systematic IP and Bus Subsystem Modeling for Platform-Based System Design [p. 560]
Kim, Y.
A Spatial Mapping Algorithm for Heterogeneous Coarse-Grained Reconfigurable Architectures [p. 363]
Kim, Y.-T.
A Systematic IP and Bus Subsystem Modeling for Platform-Based System Design [p. 560]
Klingauf, W.
TRAIN: A Virtual Transaction Layer Architecture for TLM-Based HW/SW Codesign of Synthesizable MPSoC [p. 1318]
Koch, R.
A Dynamically Reconfigurable Packet-Switched Network-on-Chip [p. 136]
Koehl, J.
DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations and Increased Defect Sensitivity in Digital, Analogue and Mixed-Signal Circuit Design [p. 387]
Koepke, A.
An Environment for Controlled Experiments with In-House Sensor Networks [p. 1108]
Kogel, T.
Virtual Prototyping of Embedded Platforms for Wireless and Multimedia [p. 488]
Kolcu, I.
Dynamic Partitioning of Processing and Memory Resources in Embedded MPSoC Architectures [p. 690]
Activity Clustering for Leakage Management in SPMs [p. 696]
Kolodny, A.
Efficient Link Capacity and QoS Design for Network-on-Chip [p. 9]
Kong, J.-T.
A Systematic IP and Bus Subsystem Modeling for Platform-Based System Design [p. 560]
Koo, H.-M.
Functional Test Generation Using Property Decompositions for Validation of Pipelined Processors [p. 1240]
Kopetz, H.
A Time-Triggered Ethernet (TTE) Switch [p. 794]
Korkmaz, P.
Ultra Efficient (Embedded) SoC Architectures Based on Probabilistic CMOS (PCMOS) Technology [p. 1110]
Kougianos, E.
Physical-Aware Simulated Annealing Optimization of Gate Leakage in Nanoscale Datapath Circuits [p. 1191]
Kozyrakis, C.
Simultaneously Improving Code Size, Performance, and Energy in Embedded Processors [p. 224]
Kraemer, S.
A Design Flow for Configurable Embedded Processors Based on Optimized Instruction Set Extension Synthesis [p. 581]
Kranitis, N.
Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications [p. 65]
Krautz, U.
Evaluating Coverage of Error Detection Logic for Soft Errors Using Formal Methods [p. 176]
Krogh, B. H.
Verifying Analog Oscillator Circuits Using Forward/Backward Abstraction Refinement [p. 257]
Kruijtzer, W.
A Unified System-Level Modeling and Simulation Environment for MPSoC Design: MPEG-4 Decoder Case Study [p. 474]
Krupp, A.
Classification Trees for Random Tests and Functional Coverage [p. 1031]
Kruseman, B.
On Test Conditions for the Detection of Open Defects [p. 896]
Kubota, H.
Large Scale RLC Circuit Analysis Using RLCG-MNA Formulation [p. 45]
Kuehlmann, A.
Building a Better Boolean Matcher and Symmetry Detector [p. 1079]
Kuenzli, S.
Combining Simulation and Formal Methods for System-Level Performance Analysis [p. 236]
Kufluoglu, H.
Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits [p. 780]
Kukkala, P.
Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications [p. 1324]
Kulkarni, C.
Memory Centric Thread Synchronization on Platform FPGAs [p. 959]
Kumar, A.
An Analytical State Dependent Leakage Power Model for FPGAs [p. 612]
Kundu, S.
A Design for Failure Analysis (DFFA) Technique to Ensure Incorruptible Signatures [p. 309]
Kuo, T.-W.
Multiprocessor Synthesis for Periodic Hard Real-Time Tasks under a Given Energy Constraint [p. 1061]
Kwon, W.-C.
A Systematic IP and Bus Subsystem Modeling for Platform-Based System Design [p. 560]

L

Lach, J.
Procrastinating Voltage Scheduling with Discrete Frequency Sets [p. 456]
Lahiri, A.
Battery-Aware Code Partitioning for a Text to Speech System [p. 672]
Lahiri, K.
Power Analysis of Mobile 3D Graphics [p. 502]
Adaptive Data Placement in an Embedded Multiprocessor Thread Library [p. 698]
Integrated Data Relocation and Bus Reconfiguration for Adaptive System-on-Chip Platforms [p. 728]
Lamberg, K.
Model-Based Testing of Automotive Electronics [p. 91]
Lambrechts, A.
Distributed Loop Controller Architecture for Multi-Threading in Uni-Threaded VLIW Processors [p. 339]
Lambrette, U.
Cross Disciplinary Aspects (4G Wireless Special Day) [p. 726]
Lambrette, U.
SoC - Fuelling the Hopes of the Mobile Industry [p. 727]
LaMeres, B. J.
Bus Stuttering: An Encoding Technique to Reduce Inductive Noise in Off-Chip Data Transmission [p. 522]
Langer, J.
New Methods and Coverage Metrics for Functional Verification [p. 1025]
Langevin, M.
Distributed Object Models for Multi-Processor SoC's, with Application to Low-Power Multimedia Wireless Systems [p. 482]
Laoutaris, N.
Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications [p. 65]
Lavigeuer, B.
Distributed Object Models for Multi-Processor SoC's, with Application to Low-Power Multimedia Wireless Systems [p. 482]
Lee, H. G.
Communication Architecture Optimization: Making the Shortest Path Shorter in Regular Networks-on-Chip [p. 712]
Lee, H.-H. S.
Microarchitectural Floorplanning under Performance and Thermal Tradeoff [p. 1288]
Lee, S.-J.
A Network-On-Chip with 3gbps/Wire Serialized On-Chip Interconnect Using Adaptive Control Schemes [p. 79]
Legat, J.-D.
Application-Specific Reconfigurable XOR-Indexing to Eliminate Cache Conflict Misses [p. 357]
Leong, P. H. W.
Hardware Efficient Architectures for Eigenvalue Computation [p. 953]
Leopold, M.
Hogthrob: Towards a Sensor Network Infrastructure for Sow Monitoring [p. 1109]
Leroux, E.
The Ultra Low-Power WiseNET System [p. 971]
Leteinturier, P.
Automotive Semi-Conductor Trend and Challenges [p. 559]
Leupers, R.
A SW Performance Estimation Framework for Early System-Level-Design Using Fine-Grained Instrumentation [p. 468]
A Design Flow for Configurable Embedded Processors Based on Optimized Instruction Set Extension Synthesis [p. 581]
Automatic ADL-Based Operand Isolation for Embedded Processors [p. 600]
An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support [p. 919]
An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration [p. 1145]
Levitan, S. P.
Nonlinear Model Order Reduction Using Remainder Functions [p. 281]
Li, D.
Efficient Assertion Based Verification Using TLM [p. 106]
Li, F.
Dynamic Partitioning of Processing and Memory Resources in Embedded MPSoC Architectures [p. 690]
Activity Clustering for Leakage Management in SPMs [p. 696]
Li, J.-F.
A Built-In Redundancy-Analysis Scheme for RAMS with 2D Redundancy Using 1D Local Bitmap [p. 53]
Li, Z.
Performance Optimization for Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems [p. 678]
Lim, S.-K.
(774)Optical Routing for 3D System-on-Package [p. 337]
3D Floorplanning with Thermal Vias [p. 878]
Microarchitectural Floorplanning under Performance and Thermal Tradeoff [p. 1288]
Lin, Y.-C.
Multiple-Fault Diagnosis Based on Single-Fault Activation and Single-Output Observation [p. 424]
Lin, K. J.
Cooptimization of Interface Hardware and Software for I/O Controllers [p. 724]
Lindsay, I.
System-Level Scheduling on Instruction Cell Based Reconfigurable Systems [p. 381]
Lingappan, L.
Test Generation for Combinational Quantum Cellular Automata (QCA) Circuits [p. 311]
Link, Z.
Reuse-Based Test Access and Integrated Test Scheduling for Network-on-Chip Systems [p. 303]
Liu, C.
Reuse-Based Test Access and Integrated Test Scheduling for Network-on-Chip Systems [p. 303]
Test Scheduling with Thermal Optimization for Network-on-Chip Systems Using Variable-Rate On-Chip Clocking [p. 652]
Liu, F.
A Practical Method to Estimate Interconnect Responses to Variabilities [p. 545]
Integrated Placement and Skew Optimization for Rotary Clocking [p. 756]
Liu, Y.
Hardware Efficient Architectures for Eigenvalue Computation [p. 953]
Liu, Y.-Y.
Crosstalk-Aware Domino Logic Synthesis [p. 1312]
Lo, D.
Distributed Object Models for Multi-Processor SoC's, with Application to Low-Power Multimedia Wireless Systems [p. 482]
Loh, G. H.
Microarchitectural Floorplanning under Performance and Thermal Tradeoff [p. 1288]
Lombardi, F.
Defect Tolerance of QCA Tiles [p. 774]
Novel Designs for Thermally Robust Coplanar Crossing in QCA [p. 786]
Lu, Y.-H.
Automatic Run-Time Selection of Power Policies for Operating Systems [p. 508]
Energy Reduction by Workload Adaptation in a Multi-Process Environment [p. 514]
Lu, Z.
Procrastinating Voltage Scheduling with Discrete Frequency Sets [p. 456]
Luk, W.
Automating Processor Customisation: Optimised Memory Access and Resource Sharing [p. 206]
Lyonnard, D.
Exploiting TLM and Object Introspection for System-Level Simulation [p. 100]
Distributed Object Models for Multi-Processor SoC's, with Application to Low-Power Multimedia Wireless Systems [p. 482]

M

Ma, Z.
Scalable Performance-Energy Trade-Off Exploration of Embedded Real-Time Systems on Multiprocessor Platforms [p. 1073]
Macii, A.
Thermal Resilient Bounded-Skew Clock Tree Optimization Methodology [p. 832]
Enabling Fine-Grain Leakage Management by Voltage Anchor Insertion [p. 868]
Macii, E.
Thermal Resilient Bounded-Skew Clock Tree Optimization Methodology [p. 832]
Enabling Fine-Grain Leakage Management by Voltage Anchor Insertion [p. 868]
Low-Power Design Tools: Are EDA Vendors Taking this Matter Seriously? [p. 1227]
Madsen, K.
Hogthrob: Towards a Sensor Network Infrastructure for Sow Monitoring [p. 1109]
Mahapatra, N. R.
Value-Based Bit Ordering for Energy Optimization of On-Chip Global Signal Buses [p. 624]
Exploiting Data-Dependent Slack Using Dynamic Multi-VDD to Minimize Energy Consumption in Datapath Circuits [p. 1001]
Mahmoodi, H.
Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating [p. 862]
Majidzadeh, V.
Arbitrary Design of High Order Noise Transfer Function for a Novel Class of Reduced-Sample- Rate Delta-Sigma-Pipeline ADCs [p. 138]
Makris, Y.
Berger Code-Based Concurrent Error Detection in Asynchronous Burst-Mode Machines [p. 71]
Mallik, A.
Smart Bit-Width Allocation for Low Power Optimization in a SystemC Based ASIC Design Environment [p. 618]
Maly, W.
Extraction of Defect Density and Size Distributions from Wafer Sort Test Results [p. 913]
Mamagkakis, S.
Dynamic Data Type Refinement Methodology for Systematic Performance-Energy Design Exploration of Network Applications [p. 740]
Automated Exploration of Pareto-Optimal Configurations in Parameterized Dynamic Memory Allocation for Embedded Systems [p. 874]
Mandal, C.
High Level Synthesis of Higher Order Continuous Time State Variable Filters with Minimum Sensitivity and Hardware Count [p. 1203]
Manet, P.
Application-Specific Reconfigurable XOR-Indexing to Eliminate Cache Conflict Misses [p. 357]
Manolache, S.
Buffer Space Optimisation with Communication Synthesis and Traffic Shaping for NoCs [p. 718]
Manolios, P.
Monolithic Verification of Deep Pipelines with Collapsed Flushing [p. 1234]
Marchal, P.
Exploring "Temperature-Aware" Design in Low-Power MPSoCs [p. 838]
Marculescu, R.
Is "Network" the Next "Big Idea" in Design? [p. 254]
Communication Architecture Optimization: Making the Shortest Path Shorter in Regular Networks-on-Chip [p. 712]
Marinissen, E. J.
Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips [p. 285]
Martens, E.
Top-Down Heterogeneous Synthesis of Analog and Mixed-Signal Systems [p. 275]
Martinez, J. A.
Nonlinear Model Order Reduction Using Remainder Functions [p. 281]
Masuda, K.
Power-Constrained Test Scheduling for Multi-Clock Domain SoCs [p. 297]
Matula, D. W.
A Formal Model and Efficient Traversal Algorithm for Generating Testbenches for Verification of IEEE Standard Floating Point Division [p. 1134]
Maurer, P. M.
Using Conjugate Symmetries to Enhance Gate-Level Simulations [p. 638]
Maxiaguine, A.
Performance Analysis of Greedy Shapers in Real-Time Systems [p. 444]
Mazumder, P.
A Logarithmic Full-Chip Thermal Analysis Algorithm Based on Multi-Layer Green's Function [p. 39]
McConaghy, T.
Double-Strength CAFFEINE: Fast Template-Free Symbolic Modeling of Analog Circuits via Implicit Canonical Form Functions and Explicit Introns [p. 269]
McFearin, L. D.
A Formal Model and Efficient Traversal Algorithm for Generating Testbenches for Verification of IEEE Standard Floating Point Division [p. 1134]
Mei, T.
Efficient AC Analysis of Oscillators Using Least-Squares Methods [p. 263]
Melly, T.
The Ultra Low-Power WiseNET System [p. 971]
Meloni, P.
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness [p. 124]
Mencer, O.
Automating Processor Customisation: Optimised Memory Access and Resource Sharing [p. 206]
Mendias, J. M.
Automated Exploration of Pareto-Optimal Configurations in Parameterized Dynamic Memory Allocation for Embedded Systems [p. 874]
Pre-Synthesis Optimization of Multiplications to Improve Circuit Performance [p. 1306]
Merentitis, A.
Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications [p. 65]
Metra, C.
Analysis of the Impact of Bus Implemented EDCs on On-Chip SSN [p. 59]
Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects [p. 170]
Meyr, H.
A SW Performance Estimation Framework for Early System-Level-Design Using Fine-Grained Instrumentation [p. 468]
Automatic ADL-Based Operand Isolation for Embedded Processors [p. 600]
4G Applications, Architectures, Design Methodology and Tools for MPSoC [p. 830]
An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support [p. 919]
Milano, M.
Communication-Aware Allocation and Scheduling Framework for Stream-Oriented Multi-Processor Systems-on-Chip [p. 3]
Milward, M.
System-Level Scheduling on Instruction Cell Based Reconfigurable Systems [p. 381]
Minz, J. R.
(774)Optical Routing for 3D System-on-Package [p. 337]
Mir, S.
Pseudorandom Functional BIST for Linear and Nonlinear MEMS [p. 664]
Mishra, P.
Functional Test Generation Using Property Decompositions for Validation of Pipelined Processors [p. 1240]
Mitra, S.
Battery-Aware Code Partitioning for a Text to Speech System [p. 672]
Mochocki, B.
Power Analysis of Mobile 3D Graphics [p. 502]
Moez, K. K.
A 10 GHz 15 dB Four-Stage Distributed Amplifier in 0.18 μm CMOS Process [p. 405]
Mohamed, O. A.
Efficient Assertion Based Verification Using TLM [p. 106]
Mohanram, K.
Large Power Grid Analysis Using Domain Decomposition [p. 27]
Mohanty, S. P.
Physical-Aware Simulated Annealing Optimization of Gate Leakage in Nanoscale Datapath Circuits [p. 1191]
Molina, M. C.
Pre-Synthesis Optimization of Multiplications to Improve Circuit Performance [p. 1306]
Molnos, A. M.
Compositional, Efficient Caches for a Chip Multi-Processor [p. 345]
Momenzadeh, M.
Defect Tolerance of QCA Tiles [p. 774]
Monchiero, M.
Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs [p. 606]
Montiel-Nelson, J. A.
Bootstrapped Full-Swing CMOS Driver for Low Supply Voltage Operation
Morin-Allory, K.
Proven Correct Monitors from PSL Specifications [p. 1246]
Motley, S. J.
Hardware Efficient Architectures for Eigenvalue Computation [p. 953]
Mueller, D.
New Methods and Coverage Metrics for Functional Verification [p. 1025]
Mueller, W.
Classification Trees for Random Tests and Functional Coverage [p. 1031]
Mueller-Glaser, K. D.
Domain Specific Model Driven Design for Automotive Electronic Control Units [p. 557]
Mukhopadhyay, S.
Circuit-Aware Device Design Methodology for Nanometer Technologies: A Case Study for Low Power SRAM Design [p. 983
Muller, O.
ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding [p. 1330]
Mundy, J.
Designing MRF Based Error Correcting Circuits for Memory Elements [p. 792]
Murali, S.
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips [p. 118]
Murgai, R.
Analyzing Timing Uncertainty in Mesh-Based Clock Architectures [p. 1097]
Murgan, T.
A Signal Theory Based Approach to the Statistical Analysis of Combinatorial Nanoelectronic Circuits [p. 632]
Myers, D.
Faster Exploration of High Level Design Alternatives Using UML for Better Partitions [p. 579]

N

Nagel, J.-L.
Architectural and Technology Influence on the Optimal Total Power Consumption [p. 989]
Nakamura, H.
An Efficient and Portable Scheduler for RTOS Simulation and its Certified Integration to SystemC [p. 1157]
Narizzano, M.
Quantifier Structure in Search Based Procedures for QBFs [p. 812]
Nauwelaers, B.
Analysis and Modeling of Power Grid Transmission Lines [p. 33]
Navabi, Z.
A Concurrent Testing Method for NoC Switches [p. 1171]
Nazarian, S.
Cell Delay Analysis Based on Rate-of-Current Change [p. 539]
Negreiros, M.
An RF Improved Loopback for Test Time Reduction [p. 646]
Nelson, J. E.
Extraction of Defect Density and Size Distributions from Wafer Sort Test Results [p. 913]
Nepal, K.
Designing MRF Based Error Correcting Circuits for Memory Elements [p. 792]
Niclass, C.
A Single Photon Avalanche Diode Array Fabricated in Deep-Submicron CMOS Technology [p. 81]
Nicolau, A.
Software Annotations for Power Optimization on Mobile Devices [p. 684]
Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors [p. 1197]
Nicolescu, B.
Soft-Error Classification and Impact Analysis on Real-Time Operating Systems [p. 182]
Nicolescu, G.
Soft-Error Classification and Impact Analysis on Real-Time Operating Systems [p. 182]
Nikolos, D.
Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding [p. 1033]
Noll, T. G.
Cross Disciplinary Aspects (4G Wireless Special Day) [p. 726]
Nooshabadi, S.
Bootstrapped Full-Swing CMOS Driver for Low Supply Voltage Operation
Nousias, I.
System-Level Scheduling on Instruction Cell Based Reconfigurable Systems [p. 381]
Núñez, A.
A Unified System-Level Modeling and Simulation Environment for MPSoC Design: MPEG-4 Decoder Case Study [p. 474]
Nuzzo, P.
A Synthesis Tool for Power-Efficient Base-Band Filter Design [p. 162]

O

Ogras, U. Y.
Communication Architecture Optimization: Making the Shortest Path Shorter in Regular Networks-on-Chip [p. 712]
Oh, K.
Dynamic Code Overlay of SDF-Modeled Programs on Low-End Embedded Systems [p. 945]
Ohlendorf, R.
Performance Evaluation for System-on-Chip Architectures Using Trace-Based Transaction Level Simulation [p. 248]
Omaña, M.
Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects [p. 170]
O'Nils, M.
Impact of Bit-Width Specification on the Memory Hierarchy for a Real-Time Video Processing System [p. 752]
Ottavi, M.
Novel Designs for Thermally Robust Coplanar Crossing in QCA [p. 786]
Ozturk, O.
Dynamic Partitioning of Processing and Memory Resources in Embedded MPSoC Architectures [p. 690]
Dynamic Scratch-Pad Memory Management for Irregular Array Access Patterns [p. 931]

P

Paci, G.
Exploring "Temperature-Aware" Design in Low-Power MPSoCs [p. 838]
Paek, Y.
A Spatial Mapping Algorithm for Heterogeneous Coarse-Grained Reconfigurable Architectures [p. 363]
Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors [p. 1197]
Palem, K. V.
Ultra Efficient (Embedded) SoC Architectures Based on Probabilistic CMOS (PCMOS) Technology [p. 1110]
Palermo, G.
Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs [p. 606]
Panainte, E. M.
Compiler-Driven FPGA-Area Allocation for Reconfigurable Computing [p. 369]
Pandey, M.
A Design Flow for Configurable Embedded Processors Based on Optimized Instruction Set Extension Synthesis [p. 581]
Pandit, S.
High Level Synthesis of Higher Order Continuous Time State Variable Filters with Minimum Sensitivity and Hardware Count [p. 1203]
Papachristou, C.
Soft Delay Error Analysis in Logic Circuits [p. 47]
Parameswaran, S.
Customization of Application Specific Heterogeneous Multi-Pipeline Processors [p. 746]
Park, C.-H.
Lens Aberration Aware Timing-Driven Placement [p. 890]
Park, J.
Dynamic Bit-Width Adaptation in DCT : Image Quality Versus Computation Energy Trade-Off [p. 520]
Park, H.-W.
Dynamic Code Overlay of SDF-Modeled Programs on Low-End Embedded Systems [p. 945]
Park, S.
Dynamic Code Overlay of SDF-Modeled Programs on Low-End Embedded Systems [p. 945]
Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors [p. 1197]
Paschalis, A.
Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications [p. 65]
Pasricha, S.
COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC [p. 700]
Passerone, R.
Functional Verification Methodology Based on Formal Interface Specification and Transactor Generation [p. 1013]
Patel, H. D.
Heterogeneous Behavioral Hierarchy for System Level Designs [p. 565]
Patil, N.
Extraction of Defect Density and Size Distributions from Wafer Sort Test Results [p. 913]
Patra, A.
High Level Synthesis of Higher Order Continuous Time State Variable Filters with Minimum Sensitivity and Hardware Count [p. 1203]
Patterson, W. R.
Designing MRF Based Error Correcting Circuits for Memory Elements [p. 792]
Paul, B. C.
Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits [p. 780]
Ultralow Power Computing with Sub-Threshold Leakage: A Comparative Study of Bulk and SOI Technologies [p. 856]
Paulin, P. G.
Distributed Object Models for Multi-Processor SoC's, with Application to Low-Power Multimedia Wireless Systems [p. 482]
Pecheux, F.
An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles [p. 94]
Pedram, M.
Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams [p. 317]
Non-Gaussian Statistical Interconnect Timing Analysis [p. 533]
Cell Delay Analysis Based on Rate-of-Current Change [p. 539]
Reducing the Sub-Threshold and Gate-Tunneling Leakage of SRAM Cells Using Dual-Vt and Dual-Tox Assignment [p. 995]
Determining the Optimal Timeout Values for a Power-Managed System Based on the Theory of Markovian Processes: Offline and Online Algorithms [p. 1128]
Low-Power Design Tools: Are EDA Vendors Taking this Matter Seriously? [p. 1227]
Peiris, V.
The Ultra Low-Power WiseNET System [p. 971]
Peng, Z.
Power Constrained and Defect-Probability Driven SoC Test Scheduling with Test Set Partitioning [p. 291]
Synthesis of Fault-Tolerant Schedules with Transparency/Performance Trade-Offs for Distributed Embedded Systems [p. 706]
Buffer Space Optimisation with Communication Synthesis and Traffic Shaping for NoCs [p. 718]
Formal Verification of SystemC Designs Using a Petri-Net Based Representation [p. 1228]
Pengg, F.
The Ultra Low-Power WiseNET System [p. 971]
Penning de Vries, R., I
EDA Challenges in the Converging Application World [p. 1]
Pereira, C. E.
Optimizing the Generation of Object-Oriented Real-Time Embedded Applications Based on the Real-Time Specification for Java [p. 806]
Pettis, N.
Automatic Run-Time Selection of Power Policies for Operating Systems [p. 508]
Pfister, P.-D.
The Ultra Low-Power WiseNET System [p. 971]
Pflanz, M.
Evaluating Coverage of Error Detection Logic for Soft Errors Using Formal Methods [p. 176]
Piguet, C.
Architectural and Technology Influence on the Optimal Total Power Consumption [p. 989]
Pilkington, C.
Exploiting TLM and Object Introspection for System-Level Simulation [p. 100]
Distributed Object Models for Multi-Processor SoC's, with Application to Low-Power Multimedia Wireless Systems [p. 482]
Pinello, C.
Exploring Trade-offs between Centralized versus Decentralized Automotive Architectures Using a Virtual Integration Environment [p. 548]
Pionteck, T.
A Dynamically Reconfigurable Packet-Switched Network-on-Chip [p. 136]
Pisano, A.
A Control Theoretic Approach to Run-Time Energy Optimization of Pipelined Processing in MPSoCs [p. 876]
Poggiali, A.
Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study [p. 15]
Polett, F.
Exploring "Temperature-Aware" Design in Low-Power MPSoCs [p. 838]
Poletti, F.
Communication-Aware Allocation and Scheduling Framework for Stream-Oriented Multi-Processor Systems-on-Chip [p. 3]
Combining Simulation and Formal Methods for System-Level Performance Analysis [p. 236]
Polian, I.
Functional Constraints vs. Test Compression in Scan-Based Delay Testing. [p. 1039]
Pomeranz, I.
Generation of Broadside Transition Fault Test Sets That Detect Four-Way Bridging Faults [p. 907]
Test Compaction for Transition Faults under Transparent-Scan [p. 1264]
Poncino, M.
Thermal Resilient Bounded-Skew Clock Tree Optimization Methodology [p. 832]
Pontarelli, S.
Novel Designs for Thermally Robust Coplanar Crossing in QCA [p. 786]
Pop, P.
Synthesis of Fault-Tolerant Schedules with Transparency/Performance Trade-Offs for Distributed Embedded Systems [p. 706]
Poucet, C.
Automated Exploration of Pareto-Optimal Configurations in Parameterized Dynamic Memory Allocation for Embedded Systems [p. 874]
Pouiklis, G.
Dynamic Data Type Refinement Methodology for Systematic Performance-Energy Design Exploration of Network Applications [p. 740]
Pozzi, L.
Automatic Identification of Application-Specific Functional Units with Architecturally Visible Storage [p. 212]
Combining Algorithm Exploration with Instruction Set Design: A Case Study in Elliptic Curve Cryptography [p. 218]
Pradhan, D. K.
Reuse-Based Test Access and Integrated Test Scheduling for Network-on-Chip Systems [p. 303]
Pravadelli, G.
On the Evaluation of Transactor-Based Verification for Reusing TLM Assertions and Testbenches at RTL [p. 1007]
Prinetto, P.
Automatic March Tests Generations for Static Linked Faults in SRAMs [p. 1258]
Prochnow, S.
Comfortable Modeling of Complex Reactive Systems [p. 577]
Pronath, M.
DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations and Increased Defect Sensitivity in Digital, Analogue and Mixed-Signal Circuit Design [p. 387]

Q

Qin, W.
Constructing Portable Compiled Instruction-Set Simulators -- An ADL-Driven Approach [p. 112]
Qu, Y.
A Parallel Configuration Model for Reducing the Run-Time Reconfiguration Overhead [p. 965]

R

Rabaey, J.
Is "Network" the Next "Big Idea" in Design? [p. 254]
Radhakrishnan, S.
Customization of Application Specific Heterogeneous Multi-Pipeline Processors [p. 746]
Radulescu, A.
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips [p. 118]
Raemy, N.
The Ultra Low-Power WiseNET System [p. 971]
Raffo, L.
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness [p. 124]
Raghavan, P.
Distributed Loop Controller Architecture for Multi-Threading in Uni-Threaded VLIW Processors [p. 339]
Raghunathan, A.
Adaptive Data Placement in an Embedded Multiprocessor Thread Library [p. 698]
Integrated Data Relocation and Bus Reconfiguration for Adaptive System-on-Chip Platforms [p. 728]
Rao, R.
An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits [p. 164]
Ravindran, B.
Lock-Free Synchronization for Dynamic Embedded Real-Time Systems [p. 438]
Raychowdhury, A.
Ultralow Power Computing with Sub-Threshold Leakage: A Comparative Study of Bulk and SOI Technologies [p. 856]
Reddy, S. M.
Generation of Broadside Transition Fault Test Sets That Detect Four-Way Bridging Faults [p. 907]
Reddy, S. M.
Analyzing Timing Uncertainty in Mesh-Based Clock Architectures [p. 1097]
Reddy, S. M.
Test Compaction for Transition Faults under Transparent-Scan [p. 1264]
Ren, Q.
Efficient Factorization of DSP Transforms Using Taylor Expansion Diagram [p. 754]
Reyes, V.
A Unified System-Level Modeling and Simulation Environment for MPSoC Design: MPEG-4 Decoder Case Study [p. 474]
Rhines, W. C.
Sociology of Design and EDA [p. 2]
Ribordy, A.
The Ultra Low-Power WiseNET System [p. 971]
Ricketts, A. J.
Priority Scheduling in Digital Microfluidics-Based Biochips [p. 329]
Ridenour, J.
Automatic Run-Time Selection of Power Policies for Operating Systems [p. 508]
Ripp, A.
DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations and Increased Defect Sensitivity in Digital, Analogue and Mixed-Signal Circuit Design [p. 387]
Robelly, J.P.
Energy Efficiency vs. Programmability Trade-off: Architectures and Design Principles [p. 587]
Rodriguez-Vazquez, A.
Systematic and Optimal Design of CMOS Two-Stage Opamps with Hybrid Cascode Compensation [p. 144]
Double-Sampling Single-Loop Sigma-Delta Modulator Topologies for Broadband Applications [p. 399]
Rolain, Y.
Systematic Stability-Analysis Method for Analog Circuits [p. 150]
Rong, P.
Determining the Optimal Timeout Values for a Power-Managed System Based on the Theory of Markovian Processes: Offline and Online Algorithms [p. 1128]
Rosenstiel, W.
Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design [p. 242]
Rosinger, P.
Minimizing Test Power in SRAM through Reduction of Pre-Charge Activity [p. 1159]
Rossello, J. L.
A Compact Model to Identify Delay Faults Due to Crosstalk [p. 902]
Rossi, D.
Analysis of the Impact of Bus Implemented EDCs on On-Chip SSN [p. 59]
Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects [p. 170]
Rouzeyre, B.
A Secure Scan Design Methodology [p. 1177]
Roy, K.
Dynamic Bit-Width Adaptation in DCT : Image Quality Versus Computation Energy Trade-Off [p. 520]
Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits [p. 780]
Ultralow Power Computing with Sub-Threshold Leakage: A Comparative Study of Bulk and SOI Technologies [p. 856]
Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating [p. 862]
Circuit-Aware Device Design Methodology for Nanometer Technologies: A Case Study for Low Power SRAM Design [p. 983]
Minimizing Ohmic Loss and Supply Voltage Variation Using a Novel Distributed Power Supply Network [p. 1116]
Roychowdhury, J.
Efficient AC Analysis of Oscillators Using Least-Squares Methods [p. 263]
Rueckert, H.
A Reconfigurable HW/SW Platform for Computation Intensive High-Resolution Real-Time Digital Film Applications [p. 194]
Rueffer, P.
A Reconfigurable HW/SW Platform for Computation Intensive High-Resolution Real-Time Digital Film Applications [p. 194]
Rufer, L.
Pseudorandom Functional BIST for Linear and Nonlinear MEMS [p. 664]
Ruffieux, D.
The Ultra Low-Power WiseNET System [p. 971]
Ruggiero, M.
Communication-Aware Allocation and Scheduling Framework for Stream-Oriented Multi-Processor Systems-on-Chip [p. 3]
Ruiz-Sautua, R.
Pre-Synthesis Optimization of Multiplications to Improve Circuit Performance [p. 1306]
Rutenbar, R. A.
Verifying Analog Oscillator Circuits Using Forward/Backward Abstraction Refinement [p. 257]

S

Safarpour, S.
On the Relation between Simulation-Based and SAT-Based Diagnosis [p. 1139]
Salminen, E.
Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications [p. 1324]
Samarah, A.
Efficient Assertion Based Verification Using TLM [p. 106]
Sánchez, E.
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis In SoCs [p. 412]
Sangiovanni-Vincentelli, A.
Is "Network" the Next "Big Idea" in Design? [p. 254]
Communication and Co-Simulation Infrastructure for Heterogeneous System Integration [p. 462]
Exploring Trade-offs between Centralized versus Decentralized Automotive Architectures Using a Virtual Integration Environment [p. 548]
FPGA Architecture Characterization for System Level Performance Analysis [p. 734]
Platform-Based Design of Wireless Sensor Networks for Industrial Applications[p. 1103]
Sarrafzadeh, M.
Layout Driven Data Communication Optimization for High Level Synthesis [p. 1185]
Sato, N.
An Efficient and Portable Scheduler for RTOS Simulation and its Certified Integration to SystemC [p. 1157]
Savaria, Y.
Soft-Error Classification and Impact Analysis on Real-Time Operating Systems [p. 182]
Scharwaechter, H.
An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support [p. 919]
Schaumont, P.
Design with Race-Free Hardware Semantics [p. 571]
Scheller, G.
A Reconfigurable HW/SW Platform for Computation Intensive High-Resolution Real-Time Digital Film Applications [p. 194]
Schillaci, M.
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis In SoCs [p. 412]
Schirner, G.
Quantitative Analysis of Transaction Level Models for the AMBA Bus [p. 230]
Schlichtmann, U.
DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations and Increased Defect Sensitivity in Digital, Analogue and Mixed-Signal Circuit Design [p. 387]
Schliebusch, O.
Automatic ADL-Based Operand Isolation for Embedded Processors [p. 600]
Schlipf, T.
(145)Task-Accurate Performance Modeling in SystemC for Real-Time Multi-Processor Architectures [p. 480]
Schoeberl, M.
A Time Predictable Java Processor [p. 800]
Schoenwald, T.
Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design [p. 242]
Schuster, C.
Architectural and Technology Influence on the Optimal Total Power Consumption [p. 989]
Schwarz, J.
Test and Reliability Challenges in Automotive Microelectronics [p. 547]
Sciuto, D.
Exploiting TLM and Object Introspection for System-Level Simulation [p. 100]
Segura, J.
A Compact Model to Identify Delay Faults Due to Crosstalk [p. 902]
Sehgal, A.
Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips [p. 285]
Seidel, H.
Energy Efficiency vs. Programmability Trade-off: Architectures and Design Principles [p. 587]
Sekar, K.
Integrated Data Relocation and Bus Reconfiguration for Adaptive System-on-Chip Platforms [p. 728]
Sergio, M.
A Single Photon Avalanche Diode Array Fabricated in Deep-Submicron CMOS Technology [p. 81]
Seshasayee, B.
Ultra Efficient (Embedded) SoC Architectures Based on Probabilistic CMOS (PCMOS) Technology [p. 1110]
Sethuraman, B.
optiMap: A Tool for Automated Generation of NoC Architectures Using Multi-Port Routers for FPGAs [p. 947]
Shang, L.
Adaptive Chip-Package Thermal Analysis for Synthesis and Design [p. 844]
Sharma, P.
Lens Aberration Aware Timing-Driven Placement [p. 890]
Shaver, D.
Next Generation Architectures Can Dramatically Reduce the 4G Deployment Cycle [p. 599]
Shekhar, N.
Equivalence Verification of Arithmetic Datapaths with Multiple Word-Length Operands [p. 824]
Shin, K.
Restructuring Field Layouts for Embedded Memory System [p. 937]
Shoaei, O.
Arbitrary Design of High Order Noise Transfer Function for a Novel Class of Reduced-Sample- Rate Delta-Sigma-Pipeline ADCs [p. 138]
Shoaei, O.
Systematic and Optimal Design of CMOS Two-Stage Opamps with Hybrid Cascode Compensation [p. 144]
Shoaei, O.
Double-Sampling Single-Loop Sigma-Delta Modulator Topologies for Broadband Applications [p. 399]
Shrikumar, H.
40Gbps De-Layered Silicon Protocol Engine for TCP Record [p. 188]
Shrivastava, A.
Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors [p. 1197]
Shukla, S.
A Hybrid Framework for Design and Analysis of Fault-Tolerant Architectures for Nanoscale Molecular Crossbar Memories [p. 335]
Design with Race-Free Hardware Semantics [p. 571]
Shukla, S. K.
Heterogeneous Behavioral Hierarchy for System Level Designs [p. 565]
Shyam, S.
Distance-Guided Hybrid Verification with GUIDO [p. 1211]
Silvano, C.
Exploiting TLM and Object Introspection for System-Level Simulation [p. 100]
Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs [p. 606]
Sim, M.-M.
Dynamic Code Overlay of SDF-Modeled Programs on Low-End Embedded Systems [p. 945]
Sinha, D.
Smart Bit-Width Allocation for Low Power Optimization in a SystemC Based ASIC Design Environment [p. 618]
Sithambaram, P.
Thermal Resilient Bounded-Skew Clock Tree Optimization Methodology [p. 832]
Skadron, K.
Procrastinating Voltage Scheduling with Discrete Frequency Sets [p. 456]
Soffke, O.
A Signal Theory Based Approach to the Statistical Analysis of Combinatorial Nanoelectronic Circuits [p. 632]
Soininen, J.-P.
A Parallel Configuration Model for Reducing the Run-Time Reconfiguration Overhead [p. 965]
Somenzi, F.
Strong Conflict Analysis for Propositional Satisfiability [p. 818]
Sommer, R.
DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations and Increased Defect Sensitivity in Digital, Analogue and Mixed-Signal Circuit Design [p. 387]
Sonza Reorda, M.
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis In SoCs [p. 412]
Sorensen, D. C.
Large Power Grid Analysis Using Domain Decomposition [p. 27]
Soudris, D.
Dynamic Data Type Refinement Methodology for Systematic Performance-Energy Design Exploration of Network Applications [p. 740]
Automated Exploration of Pareto-Optimal Configurations in Parameterized Dynamic Memory Allocation for Embedded Systems [p. 874]
Soviani, C.
Optimizing Sequential Cycles through Shannon Decomposition and Retiming [p. 1085]
Squillero, G.
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis In SoCs [p. 412]
Sridharan, J.
Modeling Multiple Input Switching of CMOS Gates in DSM Technology Using HDMR [p. 626]
Sridharan, V.
Vulnerability Analysis of L2 Cache Elements to Single Event Upsets [p. 1276]
Srinivasan, G.
Online RF Checkers for Diagnosing Multi-Gigahertz Automatic Test Boards on Low Cost ATE Platforms [p. 658]
Srinivasan, K.
A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures [p. 130]
Srinivasan, S. K.
Monolithic Verification of Deep Pipelines with Collapsed Flushing [p. 1234]
Stan, M.
Procrastinating Voltage Scheduling with Discrete Frequency Sets [p. 456]
Stanley-Marbell, P.
Adaptive Data Placement in an Embedded Multiprocessor Thread Library [p. 698]
Steiner, C.
Analysis of the Impact of Bus Implemented EDCs on On-Chip SSN [p. 59]
Steinhammer, K.
A Time-Triggered Ethernet (TTE) Switch [p. 794]
Streubuehr, M.
(145)Task-Accurate Performance Modeling in SystemC for Real-Time Multi-Processor Architectures [p. 480]
Studer, C.
Advanced Receiver Algorithms for MIMO Wireless Communication [p. 593]
Su, F.
Droplet Routing in the Synthesis of Digital Microfluidic Biochips [p. 323]
Su, Y.
Time Domain Model Order Reduction by Wavelet Collocation Method [p. 21]
Sun, K.
Large Power Grid Analysis Using Domain Decomposition [p. 27]
Sundaresan, K.
Value-Based Bit Ordering for Energy Optimization of On-Chip Global Signal Buses [p. 624]
Susin, A. A.
An RF Improved Loopback for Test Time Reduction [p. 646]
Suthar, V.
Efficient On-Line Interconnect Testing in FPGAs with Provable Detectability for Multiple Faults [p. 1165]
Sylvester, D.
An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits [p. 164]
Sze, C.-N.
Integrated Placement and Skew Optimization for Rotary Clocking [p. 756]

T

Tabuchi, N.
An Efficient and Portable Scheduler for RTOS Simulation and its Certified Integration to SystemC [p. 1157]
Tacchella, A.
Quantifier Structure in Search Based Procedures for QBFs [p. 812]
Taenzler, F.
Online RF Checkers for Diagnosing Multi-Gigahertz Automatic Test Boards on Low Cost ATE Platforms [p. 658]
Tahar, S.
Efficient Assertion Based Verification Using TLM [p. 106]
On the Numerical Verification of Probabilistic Rewriting Systems [p. 1223]
Tahoori, M. B.
Vulnerability Analysis of L2 Cache Elements to Single Event Upsets [p. 1276]
Tang, H.
Systematic Methodology for Designing Reconfigurable ΔΣ Modulator Topologies for Multimode Communication Systems [p. 393]
Tanji, Y.
Large Scale RLC Circuit Analysis Using RLCG-MNA Formulation [p. 45]
Tardieu, O.
Optimizing Sequential Cycles through Shannon Decomposition and Retiming [p. 1085]
Tast, H. W.
Evaluating Coverage of Error Detection Logic for Soft Errors Using Formal Methods [p. 176]
Taylor, V.
A Hybrid Framework for Design and Analysis of Fault-Tolerant Architectures for Nanoscale Molecular Crossbar Memories [p. 335]
Teich, J.
(145)Task-Accurate Performance Modeling in SystemC for Real-Time Multi-Processor Architectures [p. 480]
Thanailakis, A.
Dynamic Data Type Refinement Methodology for Systematic Performance-Energy Design Exploration of Network Applications [p. 740]
Theodorou, G.
Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications [p. 65]
Thiele, L.
Combining Simulation and Formal Methods for System-Level Performance Analysis [p. 236]
Performance Analysis of Greedy Shapers in Real-Time Systems [p. 444]
Thornberg, B.
Impact of Bit-Width Specification on the Memory Hierarchy for a Real-Time Video Processing System [p. 752]
Thyagaraja, S.
(774)Optical Routing for 3D System-on-Package [p. 337]
Tillich, S.
Combining Algorithm Exploration with Instruction Set Design: A Case Study in Elliptic Curve Cryptography [p. 218]
Tseng, T.-W.
A Built-In Redundancy-Analysis Scheme for RAMS with 2D Redundancy Using 1D Local Bitmap [p. 53]

U

Udayakumaran, S.
An Integrated Scratch-Pad Allocator for Affine and Non-Affine Code [p. 925]
Um, J.
A Systematic IP and Bus Subsystem Modeling for Platform-Based System Design [p. 560]

V

van de Goor, A. J.
Space of DRAM Fault Models and Corresponding Testing [p. 1252]
Van Eijndhoven, J. T. J.
Compositional, Efficient Caches for a Chip Multi-Processor [p. 345]
Vanderperren, Y.
From UML/SysML to Matlab/Simulink: Current State and Future Perspectives [p. 93]
Vandersteen, G.
Systematic Stability-Analysis Method for Analog Circuits [p. 150]
Vandierendonck, H.
Application-Specific Reconfigurable XOR-Indexing to Eliminate Cache Conflict Misses [p. 357]
Vassiliadis, S.
Compiler-Driven FPGA-Area Allocation for Reconfigurable Computing [p. 369]
Velagapudi, R.
Physical-Aware Simulated Annealing Optimization of Gate Leakage in Nanoscale Datapath Circuits [p. 1191]
Vemuri, R.
Efficient Temperature-Dependent Symbolic Sensitivity Analysis and Symbolic Performance Evaluation in Analog Circuit Synthesis [p. 283]
optiMap: A Tool for Automated Generation of NoC Architectures Using Multi-Port Routers for FPGAs [p. 947]
Veneris, A.
On the Relation between Simulation-Based and SAT-Based Diagnosis [p. 1139]
Venkataraman, G.
Integrated Placement and Skew Optimization for Rotary Clocking [p. 756]
Verbauwhede, I.
Design with Race-Free Hardware Semantics [p. 571]
Verkest, D.
Distributed Loop Controller Architecture for Multi-Threading in Uni-Threaded VLIW Processors [p. 339]
Verma, A. K.
Combining Algorithm Exploration with Instruction Set Design: A Case Study in Elliptic Curve Cryptography [p. 218]
Viaud, E.
An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles [p. 94]
Viehl, A.
Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design [p. 242]
Vierhaus, H. T.
Evaluating Coverage of Error Detection Logic for Soft Errors Using Formal Methods [p. 176]
Vijaykrishnan, N.
Priority Scheduling in Digital Microfluidics-Based Biochips [p. 329]
On-Chip Bus Thermal Analysis and Optimization [p. 850]
Villa, O.
Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs [p. 606]
Villa, T.
Efficient Minimization of Fully Testable 2-SPP Networks [p. 1300]
Viswanath, V.
Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessors [p. 496]
Vittes, M.
Microarchitectural Floorplanning under Performance and Thermal Tradeoff [p. 1288]
Volet, P.
The Ultra Low-Power WiseNET System [p. 971]
von Hanxleden, R.
Comfortable Modeling of Complex Reactive Systems [p. 577]

W

Wallentowitz, S.
A SW Performance Estimation Framework for Early System-Level-Design Using Fine-Grained Instrumentation [p. 468]
Walter, I.
Efficient Link Capacity and QoS Design for Network-on-Chip [p. 9]
Wandeler, E.
Performance Analysis of Greedy Shapers in Real-Time Systems [p. 444]
Wang, B.
A Logarithmic Full-Chip Thermal Analysis Algorithm Based on Multi-Layer Green's Function [p. 39]
Wang, C.
Disjunctive Image Computation for Embedded Software Verification [p. 1205]
Wang, F.
On-Chip Bus Thermal Analysis and Optimization [p. 850]
Wang, Q.
Lens Aberration Aware Timing-Driven Placement [p. 890]
Wang, S.
Efficient Unknown Blocking Using LFSR Reseeding [p. 1051]
Coverage Loss by Using Space Compactors in Presence of Unknown Values [p. 1053]
Wang, Z.
Test Set Enrichment Using a Probabilistic Fault Model and the Theory of Output Deviations [p. 1270]
Watanabe, T.
Large Scale RLC Circuit Analysis Using RLCG-MNA Formulation [p. 45]
Weber, K.
Evaluating Coverage of Error Detection Logic for Soft Errors Using Formal Methods [p. 176]
Weber, T.
Management of Complex Automotive Communication Networks [p. 554]
Webers, T.
Analysis and Modeling of Power Grid Transmission Lines [p. 33]
Wehn, N.
Disclosing the LDPC Code Decoder Design Space [p. 200]
Wehrmeister, M. A.
Optimizing the Generation of Object-Oriented Real-Time Embedded Applications Based on the Real-Time Specification for Java [p. 806]
Wei, W.
Coverage Loss by Using Space Compactors in Presence of Unknown Values [p. 1053]
Wei, Y.
Systematic Methodology for Designing Reconfigurable ΔΣ Modulator Topologies for Multimode Communication Systems [p. 393]
Wenk, M.
Advanced Receiver Algorithms for MIMO Wireless Communication [p. 593]
Wild, T.
Performance Evaluation for System-on-Chip Architectures Using Trace-Based Transaction Level Simulation [p. 248]
Wilke, G. R.
Analyzing Timing Uncertainty in Mesh-Based Clock Architectures [p. 1097]
Willig, A.
An Environment for Controlled Experiments with In-House Sensor Networks [p. 1108]
Wischermann, G.
A Reconfigurable HW/SW Platform for Computation Intensive High-Resolution Real-Time Digital Film Applications [p. 194]
Witte, E. M.
Automatic ADL-Based Operand Isolation for Embedded Processors [p. 600]
Wolff, F.
Soft Delay Error Analysis in Logic Circuits [p. 47]
Wolisz, A.
An Environment for Controlled Experiments with In-House Sensor Networks [p. 1108]
Wong, E.
3D Floorplanning with Thermal Vias [p. 878]
Wunderlich, H.-J.
Software-Based Self-Test of Processors under Power Constraints [p. 430]

X

Xian, C.
Energy Reduction by Workload Adaptation in a Multi-Process Environment [p. 514]
Xie, Y.
On-Chip Bus Thermal Analysis and Optimization [p. 850]
Xue, L.
Dynamic Partitioning of Processing and Memory Resources in Embedded MPSoC Architectures [p. 690]

Y

Yang, G.
Communication and Co-Simulation Infrastructure for Heterogeneous System Integration [p. 462]
Yang, H.
Efficient Temperature-Dependent Symbolic Sensitivity Analysis and Symbolic Performance Evaluation in Analog Circuit Synthesis [p. 283]
Yang, K.
Timing-Reasoning-Based Delay Fault Diagnosis [p. 418]
Yang, Y.
Adaptive Chip-Package Thermal Analysis for Synthesis and Design [p. 844]
Yang, Z.
Disjunctive Image Computation for Embedded Software Verification [p. 1205]
Yavari, M.
Systematic and Optimal Design of CMOS Two-Stage Opamps with Hybrid Cascode Compensation [p. 144]
Double-Sampling Single-Loop Sigma-Delta Modulator Topologies for Broadband Applications [p. 399]
Yi, Y.
System-Level Scheduling on Instruction Cell Based Reconfigurable Systems [p. 381]
Yoneda, T.
Power-Constrained Test Scheduling for Multi-Clock Domain SoCs [p. 297]
Yoo, H.-J.
A Network-On-Chip with 3gbps/Wire Serialized On-Chip Interconnect Using Adaptive Control Schemes [p. 79]
Yoon, J. W.
A Spatial Mapping Algorithm for Heterogeneous Coarse-Grained Reconfigurable Architectures [p. 363]
Yu, S.
Performance Optimization for Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems [p. 678]

Z

Zafalon, R.
Low-Power Design Tools: Are EDA Vendors Taking this Matter Seriously? [p. 1227]
Zanon, T.
Extraction of Defect Density and Size Distributions from Wafer Sort Test Results [p. 913]
Zaslavsky, A.
Designing MRF Based Error Correcting Circuits for Memory Elements [p. 792]
Zeng, G.
Concurrent Core Test for SoC Using Shared Test Set and Scan Chain Disable [p. 1045]
Zeng, H.
Exploring Trade-offs between Centralized versus Decentralized Automotive Architectures Using a Virtual Integration Environment [p. 548]
Zeng, X.
Time Domain Model Order Reduction by Wavelet Collocation Method [p. 21]
Zhang, H.
ALAMO: An Improved Sigma-Space Based Methodology for Modeling Process Parameter Variations in Analog Circuits [p. 156]
Zhang, L.
Statistical Timing Analysis with Path Reconvergence and Spatial Correlations [p. 528]
Zhang, Y.
Procrastinating Voltage Scheduling with Discrete Frequency Sets [p. 456]
Zhao, Y.
ALAMO: An Improved Sigma-Space Based Methodology for Modeling Process Parameter Variations in Analog Circuits [p. 156]
Zhou, D.
Time Domain Model Order Reduction by Wavelet Collocation Method [p. 21]
Zhou, H.
Smart Bit-Width Allocation for Low Power Optimization in a SystemC Based ASIC Design Environment [p. 618]
Zhou, J.
Software-Based Self-Test of Processors under Power Constraints [p. 430]
Zhou, Q.
Large Power Grid Analysis Using Domain Decomposition [p. 27]
Zhu, C.
Adaptive Chip-Package Thermal Analysis for Synthesis and Design [p. 844]
Zipf, P.
A Signal Theory Based Approach to the Statistical Analysis of Combinatorial Nanoelectronic Circuits [p. 632]
Zmily, A.
Simultaneously Improving Code Size, Performance, and Energy in Embedded Processors [p. 224]