DATE 2005 DESIGNERS' FORUM, TABLE OF CONTENTS

Sessions: [1D] [2D] [Interactive Presentations] [3D] [4D] [5D] [Interactive Presentations] [6D] [Interactive Presentations] [7D] [8D] [9D] [10D]

Designers' Forum Committee

1D: Media and Signal Processing

Moderators: W. Luk, Imperial College, UK; M. Lindwer, Philips Silicon Hive, NL

A High Quality/Low Computational Cost Technique for Block Matching Motion Estimation [p. 2]
S. López, G. Callicó, J. López, and R. Sarmiento

Hardware Acceleration of Hidden Markov Model Decoding for Person Detection [p. 8]
S. Fahmy, P. Cheung, and W. Luk

A Hardware-Friendly Wavelet Entropy Codec for Scalable Video [p. 14]
H. Eeckhaut, H. Devos, B. Schrauwen, M. Christiaens, and D. Stroobandt

A Real-Time Streaming Memory Controller [p. 20]
A. Burchard, E. Hekstra-Nowacka, and A. Chauhan

A Coprocessor for Accelerating Visual Information Processing [p. 26]
W. Stechele, S. Herrmann, L. Alvado Cárcel, and J. Lidón Simón

Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform Architectures [p. 32]
S. Silva and S. Bampi

2D: Secure and Embedded Security Systems

Moderators: A. Raghunathan, NEC Laboratories, US; L. Torres, LIRMM, FR

Hardware Engines for Bus Encryption: A Survey of Existing Techniques [p. 40]
R. Elbaz, L. Torres, G. Sassatelli, P. Guillemin, C. Anguille, M. Bardouillet, C. Buatois, and J. Rigaud

Performance Considerations for an Embedded Implementation of OMA DRM 2 [p. 46]
D. Thull and R. Sannino

A Novel Unified Architecture for Public-Key Cryptography [p. 52]
A. Cilardo, A. Mazzeo, N. Mazzocca, and L. Romano

A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs [p. 58]
K. Tiri and I. Verbauwhede

Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach [p. 64]
S. Yang, W. Wolf, N. Vijaykrishnan, D. Serpanos, and Y. Xie

Area Efficient Hardware Implementation of Elliptic Curve Cryptography by Iteratively Applying Karatsuba's Method [p. 70]
P. Langendörfer and Z. Dyka

Interactive Presentations

An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication Security [p. 76]
H. Farouk and M. Saeb

FPGA Based Agile Algorithm-on-Demand Co-Processor [p. 82]
R. Pradeep, S. Vinay, S. Burman, and V. Kamakoti

3D: Hot Topic - MPSoC Platforms for Mobile Multimedia

Organisers: W. Wolf, Princeton U, US; A. Jerraya, TIMA Laboratory, FR Moderator: W. Wolf, Princeton U, US Speakers: W. Wolf, Princeton U, US; R. Chesson, STMicroelectronics, FR; E. Flamand, STMicroelectronics, FR

Multimedia Applications of Multiprocessor Systems-on-Chips [p. 86]
W. Wolf

4D: Hot Topic . Low-Power Wireless LANs: Past, Present and Future

Organiser: T. Simunic, UC San Diego, US
Moderator: M. Renaudin, TIMA Laboratory, FR
Speakers: K. Holt, Intel Corp, US; A. Chandrakasan, Massachusetts Institute of Technology, US; T. Simunic, UC San Diego, US

Wireless LAN: Past, Present, and Future [p. 92]
K. Holt

Direct Conversion Pulsed UWB Transceiver Architecture [p. 94]
R. Blázquez, F. Lee, D. Wentzloff, B. Ginsburg, J. Powell, and A. Chandrakasan

Power Saving Techniques for Wireless LANs [p. 96]
T. Simunic

5D: Wireless Communication and Networking

Moderators: K. Torki, CMP, FR; C. Das, IMEC, BE

A Synthesizable IP Core for DVB-S2 LDPC Code Decoding [p. 100]
F. Kienle, T. Brack, and N. Wehn

picoArray Technology: The Tool's Story [p. 106]
A. Duller, D. Towner, G. Panesar, A. Gray, and W. Robbins

Queue Management in Network Processors [p. 112]
I. Papaefstathiou, G. Kornaros, T. Orphanoudakis, C. Kachris, I. Mavroidis, and A. Nikologiannis

System Level Analysis of the Bluetooth Standard [p. 118]
M. Conti and D. Moretti

C Based Hardware Design for Wireless Applications [p. 124]
A. Takach, B. Bowyer, and T. Bollaert

Hardware Accelerated Collision Detection . An Architecture and Simulation Results [p. 130]
A. Raabe, B. Bartyzel, J. Anlauf, and G. Zachmann

Interactive Presentations

Modeling of a Reconfigurable OFDM IP Block Family for an RF System Simulator [p. 136]
J. Liedes and H. Heusala

Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture [p. 138]
Y.-T. Kim, T. Kim, Y. Kim, C. Shin, E.-Y. Chung, K.-M. Choi, J.-T. Kong, S.-K. Eo

6D: Automotive

Moderators: A. Kirschbaum, Continental Teves AG & Co, DE; J. Gerlach, Robert Bosch GmbH, DE

Meeting the Embedded Design Needs of Automotive Applications [p. 142]
W. Lyons

Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs [p. 148]
A. Mayer, H. Siebert, and K. McDonald-Maier

The Integration of On-Line Monitoring and Reconfiguration Functions Using IEEE1149.4 into a Safety Critical Automotive Electronic Control Unit [p. 153]
C. Jeffrey, R. Cutajar, A. Richardson, S. Prosser, M. Lickess, and S. Riches

LC Oscillator Driver for Safety Critical Applications [p. 159]
P. Horsky

Context Sensitive Performance Analysis of Automotive Applications [p. 165]
J. Staschulat, R. Ernst, A. Schulze, and F. Wolf

AutoMoDe - Model-Based Development of Automotive Software [p. 171]
D. Ziegenbein, U. Freund, P. Braun, A. Bauer, J. Romberg, and B. Schätz

Interactive Presentation

SystemC Analysis of a New Dynamic Power Management Architecture [p. 177]
M. Conti

7D: Sensors

Moderators: R. Zafalon, STMicroelectronics, IT; W. Ecker, Infineon Technologies, DE

Exploiting Real-Time FPGA Based Adaptive Systems Technology for Real-Time Sensor Fusion in Next Generation Automotive Safety Systems [p. 180]
S. Chappell, A. Macarthur, D. Preston, D. Olmstead, B. Flint, and C. Sullivan

Platform Based Design for Automotive Sensor Conditioning [p. 186]
L. Fanucci, A. Giambastiani, A. Rocchi, F. Iozzi, and C. Marino

Realization of a Virtual Lambda Sensor on a Fixed Precision System [p. 192]
P. Amato, N. Cesario, M. Di Meglio, and F. Pirozzi

Hardware-Software Design of a Smart Sensor for Fully-Electronic DNA Hybridization Detection [p. 198]
C. Stagni, C. Guiducci, M. Lanzoni, L. Benini, and B. Ricc&oagrave;

A Tool and Methodology for AC-Stability Analysis of Continuous-Time Closed-Loop Systems [p. 204]
M. Milev and R. Burt

8D: Best of ESSCIRC 2004

Moderators: B. Courtois, TIMA Laboratory, FR; G. Gielen, KU Leuven, BE

A CMOS-Based Tactile Sensor for Continuous Blood Pressure Monitoring [p. 210]
K.-U. Kirstein, J. Sedivy, T. Salo, C. Hagleitner, T. Vancura, and A. Hierlemann

Optical Receiver IC for CD/DVD/Blue-Laser Application [p. 215]
J. Sturm, M. Leifhelm, H. Schatzmayr, S. Groiss, and H. Zimmermann

A 97mW 110 MS/s 12b Pipeline ADC Implemented in 0.18μm Digital CMOS [p. 219]
T. Andersen, A. Briskemyr, F. Telstø, J. Bjørnsen, T. Bonnerud, B. Hernes, and Ø. Moldsvor

A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13μm Digital CMOS [p. 223]
C. Sandner, M. Clara, A. Santner, T. Hartig, and F. Kuttner

9D: IP-Reuse and Reconfigurable Systems

Moderators: T. Kean, Algotronix, UK; P. Pezzati, Cadence, FR

Testing Logic Cores Using a BIST P1500 Compliant Approach: A Case of Study [p. 228]
P. Bernardi, G. Masera, F. Quaglio, and M. Sonza Reorda

MultiNoC: A Multiprocessing System Enabled by a Network on Chip [p. 234]
A. Mello, L. Möller, N. Calazans, and F. Moraes

Using Mobilize Power Management IP for Dynamic and Static Power Reduction in SoC at 130nm [p. 240]
D. Hillman

A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms [p. 247]
M. Galanis, A. Milidonis, C. Goutis, G. Theodoridis, and D. Soudris

Evaluation of SystemC Modelling of Reconfigurable Embedded Systems [p. 253]
T. Rissa, W. Luk, and A. Donlin

Hardware Support for QoS-Based Function Allocation in Reconfigurable Systems [p. 259]
M. Ullmann, W. Jin, and J. Becker

10D: Design Verification

Moderators: F. Fummi, Verona U, IT; W. Matzke, Cadence, DE

An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems [p. 266]
M. Borgatti, A. Capello, U. Rossi, F. Fummi, G. Pravadelli, J.-L. Lambert, and I. Moussa

Common Reusable Verification Environment for BCA and RTL Models [p. 272]
G. Falconeri, W. Naifer, and N. Romdhane

An Assembler Driven Verification Methodology (ADVM) [p. 278]
J. MacBeth, K. Gray, and D. Heinz

A Formal Verification Methodology for Checking Data Integrity [p. 284]
Y. Umezawa and T. Shimizu

On the Design and Verification Methodology of the Look-Aside Interface [p. 290]
A. Ahmed, A. Habibi, O. Mohamed, and S. Tahar