DATE 2005 TABLE OF CONTENTS

Sessions: [Keynote Addresses] [1A] [IP1] [1B] [1C] [IP2] [1E] [1F] [2A] [2B] [2C] [IP3] [2E] [IP4] [2F] [IP5] [3A] [IP6] [3B] [IP7] [3C] [IP8] [3E] [IP9] [3F] [4A] [IP10] [4B] [IP11] [4C] [IP12] [4E] [IP13] [4F] [IP14] [4G] [5A] [IP15] [5B] [5C] [5E] [IP16] [5F] [IP17] [5G] [5K] [6A] [IP18] [6B] [IP19] [6C] [6E] [IP20] [6F] [IP21] [6G] [IP22] [7A] [IP23] [7B] [7C] [IP24] [7E] [IP25] [7F] [IP26] [7G] [IP27] [8A] [8B] [IP28] [8C] [IP29] [8E] [IP30] [8F] [IP31] [8G] [9A] [9B] [9C] [9E] [9F] [9G] [9K] [10A] [10B] [10C] [10E] [10F] [10G]

DATE Executive Committee
Technical Program Chairs
DATE Sponsor Committee
Technical Program Committee
Reviewers
Foreword
Best Paper Awards
Tutorials
Master Courses

Volume I

Keynote Addresses

SoC in Nanoera: Challenges and Endless Possibility [p. 2]
J. Kong

Striking a New Balance in the Nanometer Era: First-Time-Right and Time-To-Market Demands Versus Technology Challenges [p. 3]
G. Hughes

1A: Partitioning and Optimisation for Reconfigurable Computing

Moderators: S. Vernalde, IMEC, BE; S. Vassiliadis, TU Delft, NL
A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures [p. 6]
N. Baradaran and P. Diniz

Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization [p. 12]
Y. Kim, M. Kiemb, C. Park, J. Jung, and K. Choi

A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores Using Dynamic Hardware/Software Partitioning [p. 18]
R. Lysecky and F. Vahid

Reconfigurable Elliptic Curve Cryptosystems on a Chip [p. 24]
R. Cheung, W. Luk, and P. Cheung

Interactive Presentations

An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs [p. 30]
R. Rodrigues and J. Cardoso

FPGA Architecture for Multi-Style Asynchronous Logic [p. 32]
N. Huot, H. Dubreuil, L. Fesquet, and M. Renaudin

1B: Hot Topic - Analogue/Digital Circuit Design in 65nm: End of the Road

Organiser/Moderator: G. Gielen, KU Leuven, BE
Speakers: G. Gielen, KU Leuven, BE; W. Dehaene, KU Leuven, BE; D. Drexelmayr, Infineon, AT; E. Janssens, ST Microelectronics, BE; T. Vucurevich, Cadence, US; K. Maex, IMEC, BE; P. Christie, Philips, NL
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [p. 36]
G. Gielen, W. Dehaene, P. Christie, D. Draxelmayr, E. Janssens, K. Maex, and T. Vucurevich

1C: SoC Design-for-Test

Moderators: E. Larsson, Linkoping U, SE; R. Dorsch, IBM, DE
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips [p. 44]
S. Goel and E. Marinissen

Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores [p. 50]
A. Sehgal, F. Liu, S. Ozev, and K. Chakrabarty

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality [p. 56]
M. Beck, O. Barondeau, M. Kaibel, F. Poehl, X. Lin, and R. Press

Interactive Presentations

Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture [p. 62]
A. Amory, M. Lubaszewski, F. Moraes, and E. Moreno

1E: Embedded Tutorial - Cross-Pollination between HW and SW - Hard Lessons for Software, and Vice Versa

Organiser: G. Martin, Tensilica, US
Moderator: L. Lavagno, Politecnico di Torino, IT
Speakers: S. Edwards, Columbia U, US; A. Dean, North Carolina State U, US; I. Oliver, Nokia, FI
The Challenges of Hardware Synthesis from C-like Languages [p. 66]
S. Edwards

Software Thread Integration and Synthesis for Real-Time Applications [p. 68]
A. Dean

Applying UML and MDA to Real Systems Design [p. 70]
I. Oliver

1F: Low Power Design with Error Tolerance

Moderators: C. Piguet, CSEM, CH; A. Macii, Politecnico di Torino, IT
Energy Bounds for Fault-Tolerant Nanoscale Designs [p. 74]
D. Marculescu

DVS for On-Chip Bus Designs Based on Timing Error Correction [p. 80]
H. Kaul, D. Sylvester, D. Blaauw, T. Mudge, and T. Austin

Joint Power Management of Memory and Disk [p. 86]
L. Cai and Y.-H. Lu

Assertion-Based Design Exploration of DVS in Network Processor Architectures [p. 92]
J. Yu, W. Wu, X. Chen, H. Hsieh, J. Yang, and F. Balarin

2A: Scheduling and Synthesis for Reconfigurable Computing

Moderators: F. Kurdahi, UC Irvine, US; C. Passerone, Politecnico di Torino, IT
Instruction Scheduling for Dynamic Hardware Configuration [p. 100]
E. Panainte, K. Bertels, and S. Vassiliadis

A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware [p. 106]
J. Resano, D. Mozos, and F. Catthoor

Optimized Generation of Data-Path from C Codes for FPGAs [p. 112]
Z. Guo, B. Buyukkurt, W. Najjar, and K. Vissers

2B: Analogue Simulation, Placement and Statistical Analysis

Moderators: G. Vandersteen, IMEC, BE; H. Graeb, TU Munich, DE
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series [p. 120]
E. Martens and G. Gielen

Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing [p. 126]
F. Liu, J. Flomenberg, D. Yasaratne, and S. Ozev

On Statistical Timing Analysis with Inter and Intra-die Variations [p. 132]
H. Mangassarian and M. Anis

Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis [p. 138]
R. Badaoui and R. Vemuri

2C: Analogue and Gigahertz Test

Moderators: A. Chatterjee, Georgia Institute of Technology, US; J. Carbonero, STMicroelectronics, FR
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits [p. 146]
K. Noguchi and M. Nagata

Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL [p. 152]
D. Keezer, C. Gray, A. Majid, and N. Taher

Noise Figure Evaluation Using Low Cost BIST [p. 158]
M. Negreiros, L. Carro, and A. Susin

Specification Test Compaction for Analog Circuits and MEMS [p. 164]
S. Biswas, R. Blanton, L. Pileggi, and P. Li

Interactive Presentations

Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach [p. 170]
V. Danelon, J. Carbonero, R. Kheriji, and S. Mir

IEEE 1149.4 Compatible ABMs for Basic RF Measurements [p. 172]
P. Syri, J. Hakkinen, and M. Moilanen

Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits [p. 174]
C. Savioli, C. Czendrodi, J. Calvano, and A. Mesquita

2E: Ubiquitous Computing: Security and Energy Aspects

Moderators: T. Basten, TU Eindhoven, NL; R. Marculescu, Carnegie Mellon U, US
Secure Embedded Processing through Hardware-Assisted Run-time Monitoring [p. 178]
D. Arora, N. Jha, S. Ravi, and A. Raghunathan

Energy-Aware Routing for E-Textile Applications [p. 184]
J.-C. Kao and R. Marculescu

LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks [p. 190]
A. Ghosh and T. Givargis

Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives [p. 196]
B. Bougard, F. Catthoor, D. Daly, A. Chandrakasan, and W. Dehaene

Interactive Presentations

Lifetime Modeling of a Sensor Network [p. 202]
V. Rai and R. Mahapatra

2F: Power Aware Design in DSM Technology

Moderators: E. Schmidt, Chip Vision Design Systems, DE; J. Haid, Infineon, DE
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs [p. 206]
J. Rosselló, V. Canals, S. Bota, J. Segura, and A. Keshavarzi

Activity Packing in FPGAs for Leakage Power Reduction [p. 212]
H. Hassan, M. Anis, A. El Daher, and M. Elmasry

Simultaneous Partitioning and Frequency Assignment for On-chip Bus Architectures [p. 218]
S. Srinivasan, L. Li, and N. Vijaykrishnan

Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits [p. 224]
S. Mukhopadhyay, S. Bhunia, and K. Roy

Interactive Presentations

Leakage-Aware Interconnect for On-Chip Network [p. 230]
Y.-F. Tsai, V. Narayaynan, Y. Xie, and M. Irwin

3A: Reconfigurability in MPSoC

Moderators: K. Goossens, Philips Research, NL; P. Ienne, EPFL, CH
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles [p. 234]
V. Nollet, T. Marescaux, P. Avasare, J.-Y. Mignolet, and D. Verkest

Symmetric Multiprocessing on Programmable Chips Made Easy [p. 240]
A. Hung, W. Bishop, and A. Kennings

A Complete Network-On-Chip Emulation Framework [p. 246]
N. Genko, G. De Micheli, D. Atienza, J. Mendias, R. Hermida, and F. Catthoor

Interactive Presentations

Low Cost Task Migration Initiation in a Heterogeneous MP-SoC [p. 252]
V. Nollet, P. Avasare, J.-Y. Mignolet, and D. Verkest

Predictable Embedding of Large Data Structures in Multiprocessor Networks-On-Chip [p. 254]
S. Stuijk, T. Basten, B. Mesman, and M. Geilen

3B: Analogue, Mixed-Signal and RF Circuits and Systems

Moderators: T. Ifström, Robert Bosch, DE; A. Rodriguez, IMSE-CNM, ES
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit [p. 258]
P. Muller, Y. Leblebici, M. Atarodi, and A. Tajalli

MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption [p. 264]
H. Tang, Y. Wei, and A. Doboli

Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance [p. 270]
C. Soens, P. Wambacq, G. Van Der Plas, and S. Donnay

Interactive Presentations

Systematic Figure of Merit Computation for the Design of Pipeline ADC [p. 277]
L. Barrandon, S. Crand, and D. Houzet

Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters [p. 279]
Y.-T. Chien, J.-H. Lou, D. Chen, G.-K. Ma, R. Rutenbar, and T. Mukherjee

3C: Reliability at the Very Deep Sub-Micron Region

Moderators: C. Metra, Bologna U, IT; R. Leveugle, TIMA Laboratory, FR
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices [p. 282]
S. Krishnaswamy, G. Viamontes, I. Markov, and J. Hayes

Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits [p. 288]
Y. Dhillon, A. Diril, and A. Chatterjee

Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques [p. 294]
O. Neiroukh and X. Song

Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown [p. 300]
J. Carter, S. Ozev, and D. Sorin

Interactive Presentations

An Accurate SER Estimation Method Based on Propagation Probability [p. 306]
G. Asadi and M. Tahoori

Techniques for Fast Transient Fault Grading Based on Autonomous Emulation [p. 308]
C. López-Ongil, M. García-Valderas, M. Portela-García, and L. Entrena-Arrontes

3E: Techniques for IP-Based Design

Moderators: R. Seepold, Carlos III de Madrid U, ES; G. Martin, Tensilica, US
TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques [p. 312]
A. Hamann and R. Ernst

Scheduling of Soft Real-Time Systems for Context-Aware Applications [p. 318]
J. Wong, F. Li, W. Liao, L. He, and M. Potkonjak

Model Reuse through Hardware Design Patterns [p. 324]
F. Rincón, F. Moya, J. Barba, and J. López

A Public-Key Watermarking Technique for IP Designs [p. 330]
A. Abdel-Hamid, S. Tahar, and E. Aboulhamid

Interactive Presentations

Design of a Virtual Component Neutral Network-on-Chip Transaction Layer [p. 336]
P. Martin

3F: HW/SW Solutions for Low Power Multimedia Systems

Moderators: J. Henkel, Karlsruhe U, DE; W. Nebel, OFFIS, DE
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing [p. 340]
S. Yardi, M. Hsiao, T. Martin, and D. Ha

HEBS: Histogram Equalization for Backlight Scaling [p. 346]
A. Iranli, H. Fatemi, and M. Pedram

Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach [p. 352]
U. Ogras and R. Marculescu

A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors [p. 358]
T. Ishihara and F. Fallah

4A: Embedded System Partitioning and Validation

Moderators: F. Petrot, Pierre et Marie Curie U, Paris VI, FR; H. Hsieh, UC Riverside, US
Design Space Exploration for Dynamically Reconfigurable Architectures [p. 366]
B. Miramond and J.-M. Delosme

A Dependability-Driven System-Level Design Approach for Embedded Systems [p. 372]
A. Jhumka, S. Klaus, and S. Huss

A Time Slice Based Scheduler Model for System Level Design [p. 378]
V. Shah, C. Passerone, L. Lavagno, and Y. Watanabe

A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation [p. 384]
J.-G. Lee, M.-K. Chung, K.-Y. Ahn, S.-H. Lee, and C.-M. Kyung

Automated Synthesis of Assertion Monitors Using Visual Specification [p. 390]
A. Gadkari and S. Ramesh

Interactive Presentations

A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms [p. 396]
G. Stitt and F. Vahid

4B: Logic Synthesis

Moderators: M. Berkelaar, Magma Design Automation, NL; T. Villa, DIEGM - Udine U, IT
Statistical Timing Based Optimization Using Gate Sizing [p. 400]
A. Agarwal, K. Chopra, and D. Blaauw

An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs [p. 406]
M. Teslenko and E. Dubrova

SAT-Based Complete Don't-Care Computation for Network Optimization [p. 412]
A. Mishchenko and R. Brayton

Efficient Solution of Language Equations Using Partitioned Representations [p. 418]
A. Mishchenko, R. Brayton, R. Jiang, T. Villa, and N. Yevtushenko

DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement [p. 424]
G. Bouesse, M. Renaudin, S. Dumont, and F. Germain

Interactive Presentations

Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition [p. 430]
A. Martinelli and E. Dubrova

Uniformly-Switching Logic for Cryptographic Hardware [p. 432]
I. Markov and D. Maslov

Exact Synthesis of 3-qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory [p. 434]
G. Yang, W. Hung, X. Song, and M. Perkowski

4C: Defect Detection and Characterisation

Moderators: R. Aitken, Artisan, US; C. Hawkins, New Mexico U, US
Memory Testing under Different Stress Conditions: An Industrial Evaluation [p. 438]
A. Majhi, M. Azimane, G. Gronthoud, M. Lousberg, S. Eichenberger, and F. Bowen

Worst-Case and Average-Case Analysis of n-Detection Test Sets [p. 444]
I. Pomeranz and S. Reddy

Defect Aware Test Patterns [p. 450]
H. Tang, G. Chen, S. Reddy, C. Wang, J. Rajski, and I. Pomeranz

Computational Intelligence Characterization Method of Semiconductor Device [p. 456]
E. Liau and D. Schmitt-Landsiedel

Interactive Presentations

A New Embedded Measurement Structure for eDRAM Capacitor [p. 462]
L. Lopez, D. Née, and J. Portal

Smart Temperature Sensor for Thermal Testing of Cell-Based ICs [p. 464]
S. Bota, M. Rosales, J. Rosseló, and J. Segura

4E: Real-Time Scheduling Defect Detection and Characterisation

Moderators: S. Baruah, North Carolina U, US; J.-D. Decotignie, CSEM, CH
An Approximation Algorithm for Energy-Efficient Scheduling on a Chip Multiprocessor [p. 468]
C.-Y. Yang, J.-J. Chen, and T.-W. Kuo

Energy-Efficient, Utility Accrual Real-Time Scheduling Under the Unimodal Arbitrary Arrival Model [p. 474]
H. Wu, B. Ravindran, and E. Jensen

Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies [p. 480]
R. Henia and R. Ernst

A New Task Model for Streaming Applications and its Schedulability Analysis [p. 486]
S. Chakraborty and L. Thiele

Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling [p. 492]
K. Albers and F. Slomka

Interactive Presentations

Unified Modeling of Complex Real-Time Control Systems [p. 498]
H. He, Y.-F. Zhong, and C.-L. Cai

4F: SoC Power Optimisation

Moderators: M. Poncino, Verona U, IT; R. Zafalon, STMicroelectronics, IT
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique [p. 502]
C. Marcon, A. Susin, N. Calazans, F. Moraes, F. Hessel, and I. Reis

Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions [p. 508]
M. Loghi and M. Poncino

Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints [p. 514]
A. Andrei, P. Eles, Z. Peng, M. Schmitz, and B. Al Hashimi

Tag Overflow Buffering: An Energy-Efficient Cache Architecture [p. 520]
P. Azzoni, M. Loghi, and M. Poncino

Interactive Presentations

Q-DPM: An Efficient Model-Free Dynamic Power Management Technique [p. 526]
M. Li, X. Wu, R. Yao, and X. Yan

Hardware Accelerated Power Estimation [p. 528]
J. Coburn, S. Ravi, and A. Raghunathan

4G: Embedded Tutorial - Platforms and Tools for Automotive System Design

Organiser/Moderator: J. Bortolazzi, DaimlerChrysler, DE
Speakers: A. Sangiovanni-Vincentelli, UC Berkeley, US; H. Brinkmeyer, IBB, DE; S. Ortmann, Carmeq, DE; J. Langenwalter, The MathWorks Inc, US/DE
Integrated Electronics in the Car and the Design Chain Evolution or Revolution? [p. 532]
A. Sangiovanni-Vincentelli

A New Approach to Component Testing [p. 534]
H. Brinkmeyer

Process Oriented Software Quality Assurance - An Experience Report in Process Improvement - OEM Perspective [p. 536]
T. Illgen and S. Ortmann

Embedded Automotive System Development Process Steer-by-Wire System [p. 538]
J. Langenwalter

5A: System Level Languages, Verification and Simulation

Moderators: P. Ellervee, TU Tallinn, ES; S. Singh, Microsoft, US
Functional Validation of System Level Static Scheduling [p. 542]
S. Abdi and D. Gajski

Defining an Enhanced RTL Semantics [p. 548]
S. Zhao and D. Gajski

RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC [p. 554]
H. Hassan, K. Sakanushi, Y. Takeuchi, and M. Imai

Design for Verification of SystemC Transaction Level Models [p. 560]
A. Habibi and S. Tahar

Interactive Presentations

Systematic Transaction Level Modeling of Embedded Systems with SystemC [p. 566]
W. Klingauf

Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures [p. 568]
S. Dasgupta and A. Yakovlev

5B: Panel Session - Semiconductor Industry Disaggregation vs. Reaggregation: Who will be the Shark?

Organiser: Y. Zorian, Virage Logic, US
Moderator: J. Barr, Buckingham Capital, US
Panellists: D. Wassung, AH&H, US; J. Ensel, Virage Logic, US; G. Stark, Synopsys, US; M. Gianfagna, eSilicon, US; K. Ruparel, Cisco Systems, US; A. de la Haye, Philips Semiconductors, NL
Semiconductor Industry Disaggregation vs Reaggregation: Who will be the Shark? [p. 572]
Y. Zorian, J. Barr, D. Wassung, J. Ensel, G. Stark, M. Gianfagna, K. Ruparel, A. de la Haye

5C: Reliable Memory Design

Moderators: D. Gizopoulos, Piraeus U, GR; M. Sonza Reorda, Politecnico di Torino, IT
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories [p. 574]
J.-F. Li, T.-W. Tseng, and C.-L. Wey

On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories [p. 580]
L. Schiano, M. Ottavi, F. Lombardi, S. Pontarelli, and A. Salsano

Increasing Register File Immunity to Transient Errors [p. 586]
G. Memik, M. Kandemir, and O. Ozturk

An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories [p. 592]
B. Gill, M. Nicolaidis, F. Wolff, C. Papachristou, and S. Garverick

5E: Execution-Time Analysis

Moderators: P. Puschner, TU Vienna, AT; G. Fohler, Malardalen U, SE
Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software [p. 600]
L. Wehmeyer and P. Marwedel

Automatic Timing Model Generation by CFG Partitioning and Model Checking [p. 606]
I. Wenzel, B. Rieder, R. Kirner, and P. Puschner

A Contribution to Branch Prediction Modeling in WCET Analysis [p. 612]
C. Burguière and C. Rochange

Interactive Presentations

Verifying Safety-Critical Timing and Memory-Usage Properties of Embedded Software by Abstract Interpretation [p. 618]
C. Ferdinand and R. Heckman

5F: Battery and Current Considerations in CMOS Design

Moderators: C. Svensson, Linkoping U, SE; A.J. Acosta Jimenez, Seville U, ES
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms [p. 622]
J. Khan and R. Vemuri

Design Method for Constant Power Consumption of Differential Logic Circuits [p. 628]
K. Tiri and I. Verbauwhede

Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling [p. 634]
L.-F. Leung, C.-Y. Tsui, and X. Hu

Low Power Oriented CMOS Circuit Optimization Protocol [p. 640]
A. Verle, X. Michel, N. Azemard, P. Maurine, and D. Auvergne

Interactive Presentations

Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction [p. 646]
T. Kitahara, N. Kawabe, F. Minami, K. Seta, and T. Furusawa

Hotspot Prevention through Runtime Reconfiguration in Network-On-Chip [p. 648]
G. Link and N. Vijaykrishnan

Power-Performance Trade-offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage [p. 650]
R. Bai, N.-S. Kim, T. Kgil, T. Mudge, and D. Sylvester

5G: Panel Session - Automotive System Architectures

Organiser/Moderator: J. Bortolazzi, DaimlerChrysler, DE
Speakers: J.-L. Maté, SiemensVDO, FR; J. Becker, Karlsruhe U, DE; C. Morgano, Microsoft Europe
Panel Session - Automotive System Architectures [p. 654]
J. Bortolazzi, J.-L. Maté, J. Becker, and C. Morgano

5K: Keynote

Automotive System Design - Challenges and Potential [p. 656]
H. Heinecke

Volume II

6A: High-Level Verification

Moderators: V. Bertacco, Michigan U, US; R. Bloem, TU Graz, AT
Effective Lower Bounding Techniques for Pseudo-Boolean Optimization [p. 660]
V. Manquinho and J. Marques-Silva

Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver [p. 666]
G. Parthasarathy, M. Iyer, and K.-T. Cheng

A Faster Counterexample Minimization Algorithm Based on Refutation Analysis [p. 672]
S. Shen, Y. Qin, and S.-K. Li

Functional Coverage Driven Test Generation for Validation of Pipelined Processors [p. 678]
P. Mishra and N. Dutt

Interactive Presentations

Pueblo: A Modern Pseudo-Boolean SAT Solver [p. 684]
H. Sheini and K. Sakallah

Space-Efficient Bounded Model Checking [p. 686]
J. Katz, Z. Hanna, and N. Dershowitz

Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking [p. 688]
G. Cabodi, M. Crivellari, S. Nocco, and S. Quer

6B: System Modelling with UML

Moderators: E. Villar, Cantabria U, ES; A. Jantsch, Royal Institute of Technology, SE
A Model-Based Approach for Executable Specifications on Reconfigurable Hardware [p. 692]
T. Schattkowsky, W. Mueller, and A. Rettberg

The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application [p. 698]
A. Chureau, Y. Savaria, and E. Aboulhamid

A SoC Design Methodology Involving a UML 2.0 Profile for SystemC_ [p. 704]
E. Riccobene, P. Scandurra, A. Rosti, and S. Bocchio

UML 2.0 Profile for Embedded System Design [p. 710]
P. Kukkala, J. Riihimäki, M. Hännikäinen, T. Hämäläinen, and K. Kronlöf

Interactive Presentations

UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design [p. 716]
Y. Vanderperren and W. Dehaene

Design Refinement for Efficient Clustering of Objects in Embedded Systems [p. 718]
W. Ahmed and D. Myers

6C: Hot Topic - Challenges in Embedded Memory Design and Test

Organiser: E. Marinissen, Philips Research Laboratories, NL
Moderator: J. Hendrickx, Philips Semiconductors, NL
Speakers: B. Prince, Memory Strategies International, US; D. Keitel-Schulz, Infineon Technologies, DE; Y. Zorian, Virage Logic, US
Challenges in Embedded Memory Design and Test [p. 722]
E. Marinissen, B. Prince, D. Keitel-Schulz, and Y. Zorian

6E: Parallel and Multithreaded Processor Architectures

Moderators: J. Teich, Erlangen-Nuremberg U, DE; R. Leupers, RWTH Aachen, DE
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures [p. 730]
A. Gangwar, M. Balakrishnan, P. Panda, and A. Kumar

Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture [p. 736]
F. Poletti, A. Poggiali, and P. Marchal

Lightweight Multitasking Support for Embedded Systems Using the Phantom Serializing Compiler [p. 742]
A. Nácul and T. Givargis

Interactive Presentations

Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications [p. 748]
D. Barretta, W. Fornaciari, M. Sami, and D. Bagni

6F: Very Deep Submicron Simulation

Moderators: M. Zwolinski, Southampton U, UK; F. Gaffiot, Ecole Centrale de Lyon, FR
An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation [p. 752]
Z. Li and C.-J. Shi

Nano-Sim: A Step Wise Equivalent Conductance Based Statistical Simulator for Nanotechnology Circuit Design [p. 758]
B. Sukhwani, U. Padmanabhan, and J. Wang

Statistical Timing Analysis Using Levelized Covariance Propagation [p. 764]
K. Kang, B. Paul, and K. Roy

A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching [p. 770]
S. Kumar, J. Li, C. Talarico, and J. Wang

Interactive Presentations

Modeling and Propagation of Noisy Waveforms in Static Timing Analysis [p. 776]
S. Nazarian, M. Pedram, E. Tuncer, T. Lin, and A. Ajami

6G: SoC Prototyping and Simulation

Moderators: M. Lajolo, NEC Laboratories, US; E. Aboulhamid, Montreal U, CA
A Network Traffic Generator Model for Fast Network-on-Chip Simulation [p. 780]
S. Mahadevan, M. Storgaard, R. Olsen, J. Sparsø, J. Madsen, F. Angiolini, and L. Benini

Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation [p. 786]
M. Reshadi and N. Dutt

Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs [p. 792]
J. Schnerr, O. Bringmann, and W. Rosenstiel

Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation [p. 798]
F. Fummi, M. Loghi, M. Poncino, S. Martini, G. Perbellini, and M. Monguzzi

Interactive Presentations

Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip [p. 804]
O. Villa, M. Monchiero, G. Palermo, P. Schaumont, and I. Verbauwhede

7A: Memory Optimisation and Clocking for SoC

Moderators: R. Hermida, Madrid U, ES; E. De Kock, Philips Research, NL
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations [p. 808]
I. Issenin and N. Dutt

Nonuniform Banking for Reducing Memory Energy Consumption [p. 814]
O. Ozturk and M. Kandemir

Systematic Analysis of Active Clock Deskewing Systems Using Control Theory [p. 820]
V. Verghase, T. Chen, and P. Young

Interactive Presentations

Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip [p. 826]
S. Kallakuri, A. Doboli, and E. Feinberg

Extended Control Flow Graph Based Performance Optimization Using Scratch-Pad Memory [p. 828]
H. Pu, M. Ling, and J. Jin

7B: Embedded Tutorial - UML for System-on-Chip Design: Current Applications and Future Perspectives

Organiser: W. Mueller, Paderborn U, DE
Moderator: G. Martin, Tensilica, US
Speakers: T. Schattkowsky, Paderborn U/C-LAB, DE; S. Mellor and J. Wolfe, Mentor Graphics, US; Q. Zhu, Fujitsu Laboratories, JP
UML 2.0 - Overview and Perspectives in SoC Design [p. 832]
T. Schattkowsky

Why Systems-on-Chip Needs More UML like a Hole in the Head [p. 834]
S. Mellor, J. Wolfe, and C. McCausland

Integrating UML into SoC Design Process [p. 836]
Q. Zhu, R. Oishi, T. Hasegawa, and T. Nakata

7C: Test Power Reduction and Diagnosis

Moderators: P. Prinetto, Politecnico di Torino, IT; C. Papachristou, Case Western Reserve U, US
Rapid Generation of Thermal-Safe Test Schedules [p. 840]
P. Rosinger, B. Al-Hashimi, and K. Chakrabarty

Simultaneous Reduction of Dynamic and Static Power in Scan Structures [p. 846]
S. Sharifi, J. Jaffari, M. Hosseinabady, A. Afzali-Kusha, and Z. Navabi

A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs [p. 852]
B. Wang, A. Ivanov, and Y. Wu

Interactive Presentations

New Schemes for Self-Testing RAM [p. 858]
G. Bodean, D. Bodean, and A. Labunetz

At-Speed Logic BIST for IP Cores [p. 860]
B. Cheon, E. Lee, L.-T. Wang, X. Wen, P. Hsu, J. Cho, J. Park, H. Chao, and S. Wu

7E: Scheduling and Memory Optimisation for Multiprocessor Embedded Systems

Moderators: J. Madsen, TU Denmark, DK; J. Lopéz, Castilla-la Mancha U, ES
Design Optimization of Time- and Cost-Constrained Fault-Tolerant Distributed Embedded Systems [p. 864]
V. Izosimov, P. Pop, P. Eles, and Z. Peng

Locality-Aware Process Scheduling for Embedded MPSoCs [p. 870]
M. Kandemir and G. Chen

A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms [p. 876]
T. Kempf, M. Doerper, R. Leupers, G. Ascheid, H. Meyr, T. Kogel, and B. Vanthournout

Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems [p. 882]
O. Ozturk, H. Saputra, M. Kandemir, and I. Kolcu

System Synthesis for Networks of Programmable Blocks [p. 888]
R. Mannion, H. Hsieh, S. Cotterell, and F. Vahid

Interactive Presentations

Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks [p. 894]
T. Streichert, C. Haubelt, and J. Teich

Synchronization Processor Synthesis for Latency Insensitive Systems [p. 896]
P. Bomel, E. Martin, and E. Boutillon

Thermal-Aware Task Allocation and Scheduling for Embedded Systems [p. 898]
W.-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, and M. Irwin

7F: Layout Issues

Moderators: J. Koehl, IBM Microelectronics, DE; J. Lienig, TU Dresden, DE
An Improved Multi-Level Framework for Force-Directed Placement [p. 902]
K. Vorwerk and A. Kennings

Bright-Field AAPSM Conflict Detection and Correction [p. 908]
X. Xu, A. Kahng, S. Sinha, C. Chiang, and A. Zelikovsky

Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules [p. 914]
H. Wang, M. Miranda, W. Dehaene, F. Catthoor, and K. Maex

Interactive Presentations

TSUNAMI: An Integrated Timing-Driven Place and Route Research Platform [p. 920]
C. Alexandre, H. Clément, J.-P. Chaput, M. Sroka, C. Masson, and R. Escassut

Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric [p. 922]
A. Bhaduri and R. Vemuri

7G: Quantifying Architecture Trade-Off

Moderators: L. Lavagno, Politecnico di Torino, IT; W. Kruijtzer, Philips Research, IT
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies [p. 926]
A. Datta, S. Bhunia, S. Mukhopadhyay, N. Banerjee, and K. Roy

Compositional Memory Systems for Multimedia Communicating Tasks [p. 932]
A. Molnos, S. Cotofana, M. Heijligers, and J. Van Eijndhoven

Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes [p. 938]
J. Kruse, C. Thomsen, R. Ernst, T. Volling, and T. Spengler

Interactive Presentations

A New System Design Methodology for Wire Pipelined SoC [p. 944]
M. Casu and L. Macchiarulo

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck [p. 946]
M. Dasygenis, D. Soudris, A. Thanailakis, E. Brockmeyer, B. Durinck, and F. Catthoor

8A: Panel Session - Is There a Market for SystemC Tools?

Organiser/Moderator: W. Rosenstiel, Tuebingen U, DE
Panellists: R. Bergamaschi, IBM, US; F. Ghenassia, STMicroelectronics, FR; T. Groetker, Synopsys, DE; M. Kawarabayashi, NEC, JP; M. van Lier, Philips Semiconductors, NL; A. Mayer, Infineon Technologies, DE; M. Meredith, Forte Design Systems, US; M. Milligan, CoWare, US; S. Swan, Cadence, US
Is There a Market for SystemC Tools? [p. 950]
W. Rosenstiel, R. Bergamaschi, F. Ghenassia, T. Groetker, M. Kawarabayashi, A. Mayer, M. Meredith, and M. Milligan

8B: Interconnect Solutions: Timing, Noise, and Process Variations

Moderators: P. Feldmann, IBM TJ Watson Research Center, US; D. Luca, MIT, US
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model [p. 952]
L. Zhang, W. Chen, Y. Hu, and C.C.-P. Chen

Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction [p. 958]
P. Li, F. Liu, S. Nassif, and L. Pileggi

Stochastic Power Grid Analysis Considering Process Variations [p. 964]
P. Ghanta, S. Vrudhula, J. Wang, and R. Panda

Buffer Insertion Considering Process Variation [p. 970]
J. Xiong, K. Tam, and L. He

EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation [p. 976]
B. Wang and P. Mazumder

Interactive Presentations

Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis [p. 982]
C. Forzan and D. Pandini

Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions [p. 984]
A. Chandy and T. Chen

Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization [p. 986]
P. Zuber, A. Windschiegl, R. de Otálora, W. Stechele, and A. Herkersdorf

8C: Advances in Pattern Generation for Fault Detection and Diagnosis

Moderators: R. Galivanche, Intel, US; H. Obermeir, Infineon Technologies, DE
Implicit and Exact Path Delay Fault Grading in Sequential Circuits [p. 990]
V. Kumar, S. Tragoudas, R. Jayabharathi, and S. Chakravarty

Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs [p. 996]
Y.-S. Yang, A. Veneris, P. Thadikaran, and S. Venkataraman

Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation [p. 1002]
K. Chandrasekar and M. Hsiao

The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits [p. 1008]
I. Pomeranz and S. Reddy

Diagnostic and Detection Fault Collapsing for Multiple Output Circuits [p. 1014]
R. Sandireddy and V. Agrawal

Interactive Presentations

Framework for Fault Analysis and Test Generation in DRAMs [p. 1020]
Z. Al-Ars, S. Hamdioui, A. Van De Goor, and G. Mueller

Mutation Sampling Technique for the Generation of Structural Test Data [p. 1022]
M. Scholivé, V. Beroulle, C. Robach, M. Flottes, and B. Rouzeyre

8E: Embedded Software Technology

Moderators: J. Sztipanovits, ISIS Vanderbilt U, US; P. Kajfasz, Thales Communication, FR
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing [p. 1026]
M. Kandemir, F. Li, G. Chen, G. Chen, and O. Ozturk

BB-GC: Basic-Block Level Garbage Collection [p. 1032]
O. Ozturk, M. Kandemir, and M. Irwin

Fine Grain QoS Control for Multimedia Application Software [p. 1038]
J. Combaz, J.-C. Fernandez, J. Sifakis, and T. Lepley

Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development [p. 1044]
M. Baleani, A. Ferrari, L. Mangeruca, A. Sangiovanni-Vincentelli, U. Freund, E. Schlenker, and H.-J. Wolff

galsC: A Language for Event-Driven Embedded Systems [p. 1050]
E. Cheong and J. Liu

Interactive Presentations

Compiler-Directed Instruction Duplication for Soft Error Detection [p. 1056]
J. Hu, F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan, and M. Irwin

OS Debugging Method Using a Lightweight Virtual Machine Monitor [p. 1058]
T. Takeuchi

Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications [p. 1060]
N. Kavvadias and S. Nikolaidis

8F: Advanced Analogue Performance Modelling

Moderators: L. Hedrich, Frankfurt U, DE; E. Martens, KU Leuven, BE
Mixing Global and Local Competition in Genetic Optimization Based Design Space Exploration of Analog Circuits [p. 1064]
A. Somani, P. Chakrabarti, and A. Patra

Efficient Multiobjective Synthesis of Analog Circuits Using Hierarchical Pareto-Optimal Performances Hypersurfaces [p. 1070]
T. Eeckelaert, T. McConaghy, and G. Gielen

Estimating Scalable Common-Denominator Laplace-Domain MIMO Models in an Errors-in-Variables Framework [p. 1076]
G. Vandersteen, L. De Locht, S. Jenei, Y. Rolain, and R. Pintelon

CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming [p. 1082]
T. McConaghy, T. Eeckelaert, and G. Gielen

Interactive Presentations

A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling [p. 1088]
M. Ding and R. Vemuri

8G: Hot Topic - Biochips: Principles and Application

Organiser/Moderator: C. Paulus, Infineon Technologies, DE
New Perspectives and Opportunities from the Wild West of Microelectronic Biochips [p. 1092]
N. Manaresi, G. Medoro, M. Abonnenc, V. Auger, P. Vulto, A. Romani, L. Altomare, M. Tartagni, and R. Guerrieri

9A: Efficient SAT Based Verification

Moderators: R. Drechsler, Bremen U, DE; E. Giunchiglia, DIST - Genova U, IT
Verification of Embedded Memory Systems Using Efficient Memory Modeling [p. 1096]
M. Ganai, A. Gupta, and P. Ashar

An Efficient Sequential SAT Solver with Improved Search Strategies [p. 1102]
F. Lu, M. Iyer, G. Parthasarathy, L.-C. Wang, K.-T. Cheng, and K. Chen

Considering Circuit Observability Don't Cares in CNF Satisfiability [p. 1108]
Z. Fu, Y. Yu, and S. Malik

9B: Embedded Tutorial - How Do They Manage Designing Complex SoC?

Organiser/Moderator: Y.-L. Lin, National Tsing Hua U, Taiwan, ROC
Speakers: J.-Y Lin, Global UniChip Corp, Taiwan, ROC; L.-G. Chen, ERSO/ITRI & National Taiwan U, ROC; C.-W. Wu, National Tsing Hua U, Taiwan, ROC
Integration, Verification and Layout of a Complex Multimedia SOC [p. 1116]
C.-L. Chen, J.-Y. Lin, and Y.-L. Lin

JPEG, MPEG-4, and H.264 Codec IP Development [p. 1118]
C.-J. Lian, Y.-W. Huang, H.-C. Fang, Y.-C. Chang, and L.-G. Chen

SOC Testing Methodology and Practice [p. 1120]
C.-W. Wu

9C: Test Pattern Compression and Delay Test Schemes

Moderators: F. Hapke, Philips Semiconductors, DE; M. Flottes, LIRMM, FR
Evolutionary Optimization in Code-Based Test Compression [p. 1124]
I. Polian, A. Czutro, and B. Becker

Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination [p. 1130]
K. Balakrishnan and N. Touba

A Novel Low-Overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application [p. 1136]
S. Bhunia, H. Mahmoodi, A. Raychowdhury, and K. Roy

Hybrid BIST Based on Repeating Sequences and Cluster Analysis [p. 1142]
L. Li and K. Chakrabarty

9E: Compiler/Architecture Codesign

Moderators: H. van Sommeren, ACE Associated Compiler Experts, NL; P. Marwedel, Dortmund U, DE
C Compiler Retargeting Based on Instruction Semantics Models [p. 1150]
J. Ceng, M. Hohenauer, G. Braun, R. Leupers, G. Ascheid, and H. Meyr

A Constraint Network Based Approach to Memory Layout Optimization [p. 1156]
G. Chen, M. Kandemir, and M. Karakoy

Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access [p. 1162]
M. Absar and F. Catthoor

Structural Testing Based on Minimum Kernels [p. 1168]
E. Dubrova

9F: Network-on-Chip Design Flows

Moderators: G. Nicolescu, Ecole Polytechnique de Montréal, CA; W. Cesário, TIMA Laboratory, FR
An Application-Specific Design Methodology for STbus Crossbar Generation [p. 1176]
S. Murali and G. De Micheli

A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification [p. 1182]
K. Goossens, J. Dielissen, O. Gangwal, S. Gonzalez Pestana, A. Radulescu, and E. Rijpkema

xpipes Lite: A Synthesis Oriented Design Library for Networks on Chips [p. 1188]
S. Stergiou, G. De Micheli, F. Angiolini, D. Bertozzi, S. Carta, and L. Raffo

9G: Biochips and Quantum Computing

Moderators: V. Narayanan, Penn State U, US; M. Poncino, Politecnico di Torino, IT
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration [p. 1196]
F. Su, K. Chakrabarty, and V. Pamula

Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips [p. 1202]
F. Su and K. Chakrabarty

Quantum Circuit Simplification Using Templates [p. 1208]
D. Maslov, C. Young, D. Miller, and G. Dueck

Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths [p. 1214]
K. Kim, K. Wu, and R. Karri

9K: CMOS-Based Biosensor Arrarys

Moderator: C. Paulus, Infineon Technologies, DE
CMOS-Based Biosensor Arrays [p. 1222]
R. Thewes, C. Paulus, M. Schienle, F. Hofmann, A. Frey, R. Brederlow, M. Augustyniak, M. Jenkner, B. Eversmann, P. Schindler-Bauer, M. Atzesberger, B. Holzapfl, G. Beer, T. Haneder, and H.-C. Hanke

10A: Efficient Network-on-Chip Architectures

Moderators: G. De Micheli, EPFL Lausanne, CH; D. Bertozzi, DEIS - Bologna U, IT
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip [p. 1226]
T. Bjerregaard and J. Sparsø

A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips [p. 1232]
W.-D. Weber, I. Swarbrick, J. Chou, and D. Wingard

A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks [p. 1238]
H. Wang, L.-S. Peh, and S. Malik

10B: Architectural Synthesis and Design Space Exploration

Moderators: C. Silvano, Politecnico di Milano, IT; P. Pop, Linkoping U, SE
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement [p. 1246]
P. Biswas, S. Banerjee, N. Dutt, L. Pozzi, and P. Ienne

Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis [p. 1252]
R. Ruiz-Sautua, M. Molina, J. Mendías, and R. Hermida

Reliability-Centric High-Level Synthesis [p. 1258]
S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, and Y. Xie

PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors [p. 1264]
A. Shrivastava, A. Nicolau, N. Dutt, and E. Earlie

10C: Concurrent Error Detection and Correction

Moderators: S. Piestrak, TU Wroclaw, PL; M. Nicolaidis, iRoC, FR
Concurrent Error Detection in Asynchronous Burst-Mode Controllers [p. 1272]
S. Almukhaizim and Y. Makris

Reliable System Specification for Self-Checking Data-Paths [p. 1278]
C. Bolchini, F. Salice, D. Sciuto, and L. Pomante

Evaluation of Error-Resilience for Reliable Compression of Test Data [p. 1284]
H. Hashempour, L. Schiano, and F. Lombardi

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-Based FPGAs [p. 1290]
F. Kastensmidt, L. Sterpone, M. Sonza Reorda, and L. Carro

10E: Formal Verification of Processor Architecture and DSP Programs

Moderators: D. Stoffel, Kaiserslautern U, DE; G. Cabodi, Politecnico di Torino, IT
Automatic Formal Verification of Fused-Multiply-Add FPUs [p. 1298]
C. Jacobi, K. Weber, V. Paruthi, and J. Baumgartner

Refinement Maps for Efficient Verification of Processor Models [p. 1304]
P. Manolios and S. Srinivasan

Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code [p. 1310]
K. Shashidhar, F. Catthoor, M. Bruynooghe, and G. Janssens

10F: Interconnect Optimisation

Moderators: D. Stroobandt, Ghent U, BE; M. Berkelaar, Magma Design Automation, NL
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission [p. 1318]
B. LaMeres and S. Khatri

An O(bn2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types [p. 1324]
Z. Li and W. Shi

RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power [p. 1330]
X. Liu, Y. Peng, and M. Papaefthymiou

10G: Hot Topic - Silicon Based Biochips

Organiser/Moderator: C. Paulus, Infineon Technologies, DE
Speakers: B. Vigna, STMicroelectronics, IT; R. Campagnolo, CEA G/LETI, FR; K.-U. Kirstein, ETH Zurich, CH
eMICAM: A New Generation of Active DNA Chip with in Situ Electrochemical Detection [p. 1338]
R. Campagnolo

Cantilever-Based Biosensors in CMOS Technology [p. 1340]
K.-U. Kirstein, Y. Li, M. Zimmermann, C. Vancura, T. Volden, W. Song, J. Lichtenberg, and A. Hierlemannn