DATE 2005 SESSION INDEX
Keynote Addresses
1A:
Partitioning and Optimisation for Reconfigurable Computing
Interactive Presentations
1B:
Hot Topic - Analogue/Digital Circuit Design in 65nm: End of the Road
1C:
SoC Design-for-Test
Interactive Presentations
1E:
Embedded Tutorial - Cross-Pollination between HW and SW - Hard Lessons for Software, and Vice Versa
1F:
Low Power Design with Error Tolerance
2A:
Scheduling and Synthesis for Reconfigurable Computing
2B:
Analogue Simulation, Placement and Statistical Analysis
2C:
Analogue and Gigahertz Test
Interactive Presentations
2E:
Ubiquitous Computing: Security and Energy Aspects
Interactive Presentations
2F:
Power Aware Design in DSM Technology
Interactive Presentations
3A:
Reconfigurability in MPSoC
Interactive Presentations
3B:
Analogue, Mixed-Signal and RF Circuits and Systems
Interactive Presentations
3C:
Reliability at the Very Deep Sub-Micron Region
Interactive Presentations
3E:
Techniques for IP-Based Design
Interactive Presentations
3F:
HW/SW Solutions for Low Power Multimedia Systems
4A:
Embedded System Partitioning and Validation
Interactive Presentations
4B:
Logic Synthesis
Interactive Presentations
4C:
Defect Detection and Characterisation
Interactive Presentations
4E:
Real-Time Scheduling Defect Detection and Characterisation
Interactive Presentations
4F:
Power Optimisation
Interactive Presentations
4G:
Embedded Tutorial - Platforms and Tools for Automotive System Design
5A:
System Level Languages, Verification and Simulation
Interactive Presentations
5B:
Panel Session - Semiconductor Industry Disaggregation vs. Reaggregation: Who will be the Shark?
5C:
Reliable Memory Design
5E:
Execution-Time Analysis
Interactive Presentations
5F:
Battery and Current Considerations in CMOS Design
Interactive Presentations
5G:
Panel Session - Automotive System Architectures
5K:
Keynote
6A:
High-Level Verification
Interactive Presentations
6B:
System Modelling with UML
Interactive Presentations
6C:
Hot Topic - Challenges in Embedded Memory Design and Test
6E:
Parallel and Multithreaded Processor Architectures
Interactive Presentations
6F:
Very Deep Submicron Simulation
Interactive Presentations
6G:
SoC Prototyping and Simulation
Interactive Presentations
7A:
Memory Optimisation and Clocking for SoC
Interactive Presentations
7B:
Embedded Tutorial - UML for System-on-Chip Design: Current Applications and Future Perspectives
7C:
Test Power Reduction and Diagnosis
Interactive Presentations
7E:
Scheduling and Memory Optimisation for Multiprocessor Embedded Systems
Interactive Presentations
7F:
Layout Issues
Interactive Presentations
7G:
Quantifying Architecture Trade-Off
Interactive Presentations
8A:
Panel Session - Is There a Market for SystemC Tools?
8B:
Interconnect Solutions: Timing, Noise, and Process Variations
Interactive Presentations
8C:
Advances in Pattern Generation for Fault Detection and Diagnosis
Interactive Presentations
8E:
Embedded Software Technology
Interactive Presentations
8F:
Advanced Analogue Performance Modelling
Interactive Presentations
8G:
Hot Topic - Biochips: Principles and Application
9A:
Efficient SAT Based Verification
9B:
Embedded Tutorial - How Do They Manage Designing Complex SoC?
9C:
Test Pattern Compression and Delay Test Schemes
9E:
Compiler/Architecture Codesign
9F:
Network-on-Chip Design Flows
9G:
Biochips and Quantum Computing
9K:
CMOS-Based Biosensor Arrarys
10A:
Efficient Network-on-Chip Architectures
10B:
Architectural Synthesis and Design Space Exploration
10C:
Concurrent Error Detection and Correction
10E:
Formal Verification of Processor Architecture and DSP Programs
10F:
Interconnect Optimisation
10G:
Hot Topic - Silicon Based Biochips