DATE 2005 AUTHOR INDEX

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [V] [W] [X] [Y] [Z]

A

Abdel-Hamid, A.
A Public-Key Watermarking Technique for IP Designs [p. 330]
Abdi, S.
Functional Validation of System Level Static Scheduling [p. 542]
Abonnenc, M.
New Perspectives and Opportunities from the Wild West of Microelectronic Biochips [p. 1092]
Aboulhamid, E.
A Public-Key Watermarking Technique for IP Designs [p. 330]
The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application [p. 698]
Absar, M.
Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access [p. 1162]
Afzali-Kusha, A.
Simultaneous Reduction of Dynamic and Static Power in Scan Structures [p. 846]
Agarwal, A.
Statistical Timing Based Optimization Using Gate Sizing [p. 400]
Agrawal, V.
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits [p. 1014]
Ahmed, W.
Design Refinement for Efficient Clustering of Objects in Embedded Systems [p. 718]
Ahn, K.-Y.
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation [p. 384]
Ajami, A.
Modeling and Propagation of Noisy Waveforms in Static Timing Analysis [p. 776]
Al-Ars, Z.
Framework for Fault Analysis and Test Generation in DRAMs [p. 1020]
Albers, K.
Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling [p. 492]
Alexandre, C.
TSUNAMI: An Integrated Timing-Driven Place and Route Research Platform [p. 920]
Al-Hashimi, B.
Rapid Generation of Thermal-Safe Test Schedules [p. 840]
Almukhaizim, S.
Concurrent Error Detection in Asynchronous Burst-Mode Controllers [p. 1272]
Altomare, L.
New Perspectives and Opportunities from the Wild West of Microelectronic Biochips [p. 1092]
Amory, A.
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture [p. 62]
Andrei, A.
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints [p. 514]
Angiolini, F.
A Network Traffic Generator Model for Fast Network-on-Chip Simulation [p. 780]
xpipes Lite: A Synthesis Oriented Design Library for Networks on Chips [p. 1188]
Anis, M.
On Statistical Timing Analysis with Inter and Intra-die Variations [p. 132]
Activity Packing in FPGAs for Leakage Power Reduction [p. 212]
Arora, D.
Secure Embedded Processing through Hardware-Assisted Run-time Monitoring [p. 178]
Arvas, E.
Reliability-Centric High-Level Synthesis [p. 1258]
Asadi, G.
An Accurate SER Estimation Method Based on Propagation Probability [p. 306]
Ascheid, G.
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms [p. 876]
Ascheid, G.
C Compiler Retargeting Based on Instruction Semantics Models [p. 1150]
Ashar, P.
Verification of Embedded Memory Systems Using Efficient Memory Modeling [p. 1096]
Atarodi, M.
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit [p. 258]
Atienza, D.
A Complete Network-On-Chip Emulation Framework [p. 246]
Atzesberger, M.
CMOS-Based Biosensor Arrays [p. 1222]
Auger, V.
New Perspectives and Opportunities from the Wild West of Microelectronic Biochips [p. 1092]
Augustyniak, M.
CMOS-Based Biosensor Arrays [p. 1222]
Austin, T.
DVS for On-Chip Bus Designs Based on Timing Error Correction [p. 80]
Auvergne, D.
Low Power Oriented CMOS Circuit Optimization Protocol [p. 640]
Avasare, P.
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles [p. 234]
Low Cost Task Migration Initiation in a Heterogeneous MP-SoC [p. 252]
Azemard, N.
Low Power Oriented CMOS Circuit Optimization Protocol [p. 640]
Azimane, M.
Memory Testing under Different Stress Conditions: An Industrial Evaluation [p. 438]
Azzoni, P.
Tag Overflow Buffering: An Energy-Efficient Cache Architecture [p. 520]

B

Badaoui, R.
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis [p. 138]
Bagni, D.
Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications [p. 748]
Bai, R.
Power-Performance Trade-offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage [p. 650]
Balakrishnan, K.
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination [p. 1130]
Balakrishnan, M.
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures [p. 730]
Balarin, F.
Assertion-Based Design Exploration of DVS in Network Processor Architectures [p. 92]
Baleani, M.
Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development [p. 1044]
Banerjee, N.
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies [p. 926]
Banerjee, S.
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement [p. 1246]
Baradaran, N.
A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures [p. 6]
Barba, J.
Model Reuse through Hardware Design Patterns [p. 324]
Barondeau, O.
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality [p. 56]
Barr, J.
Semiconductor Industry Disaggregation vs Reaggregation: Who will be the Shark? [p. 572]
Barrandon, L.
Systematic Figure of Merit Computation for the Design of Pipeline ADC [p. 277]
Barretta, D.
Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications [p. 748]
Basten, T.
Predictable Embedding of Large Data Structures in Multiprocessor Networks-On-Chip [p. 254]
Baumgartner, J.
Automatic Formal Verification of Fused-Multiply-Add FPUs [p. 1298]
Beck, M.
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality [p. 56]
Becker, B.
Evolutionary Optimization in Code-Based Test Compression [p. 1124]
Becker, J.
Panel Session - Automotive System Architectures [p. 654]
Beer, G.
CMOS-Based Biosensor Arrays [p. 1222]
Benini, L.
A Network Traffic Generator Model for Fast Network-on-Chip Simulation [p. 780]
Bergamaschi, R.
Is There a Market for SystemC Tools? [p. 950]
Beroulle, V.
Mutation Sampling Technique for the Generation of Structural Test Data [p. 1022]
Bertels, K.
Instruction Scheduling for Dynamic Hardware Configuration [p. 100]
Bertozzi, D.
xpipes Lite: A Synthesis Oriented Design Library for Networks on Chips [p. 1188]
Bhaduri, A.
Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric [p. 922]
Bhunia, S.
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits [p. 224]
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies [p. 926]
A Novel Low-Overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application [p. 1136]
Bishop, W.
Symmetric Multiprocessing on Programmable Chips Made Easy [p. 240]
Biswas, P.
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement [p. 1246]
Biswas, S.
Specification Test Compaction for Analog Circuits and MEMS [p. 164]
Bjerregaard, T.
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip [p. 1226]
Blaauw, D.
DVS for On-Chip Bus Designs Based on Timing Error Correction [p. 80]
Statistical Timing Based Optimization Using Gate Sizing [p. 400]
Blanton, R.
Specification Test Compaction for Analog Circuits and MEMS [p. 164]
Bocchio, S.
A SoC Design Methodology Involving a UML 2.0 Profile for SystemC_ [p. 704]
Bodean, D.
New Schemes for Self-Testing RAM [p. 858]
Bodean, G.
New Schemes for Self-Testing RAM [p. 858]
Bolchini, C.
Reliable System Specification for Self-Checking Data-Paths [p. 1278]
Bomel, P.
Synchronization Processor Synthesis for Latency Insensitive Systems [p. 896]
Bortolazzi, J.
Panel Session - Automotive System Architectures [p. 654]
Bota, S.
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs [p. 206]
Bota, S.
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs [p. 464]
Bouesse, G.
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement [p. 424]
Bougard, B.
Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives [p. 196]
Boutillon, E.
Synchronization Processor Synthesis for Latency Insensitive Systems [p. 896]
Bowen, F.
Memory Testing under Different Stress Conditions: An Industrial Evaluation [p. 438]
Braun, G.
C Compiler Retargeting Based on Instruction Semantics Models [p. 1150]
Brayton, R.
SAT-Based Complete Don't-Care Computation for Network Optimization [p. 412]
Efficient Solution of Language Equations Using Partitioned Representations [p. 418]
Brederlow, R.
CMOS-Based Biosensor Arrays [p. 1222]
Bringmann, O.
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs [p. 792]
Brinkmeyer, H.
A New Approach to Component Testing [p. 534]
Brockmeyer, E.
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck [p. 946]
Bruynooghe, M.
Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code [p. 1310]
Burguière, C.
A Contribution to Branch Prediction Modeling in WCET Analysis [p. 612]
Buyukkurt, B.
Optimized Generation of Data-Path from C Codes for FPGAs [p. 112]

C

Cabodi, G.
Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking [p. 688]
Cai, C.-L.
Unified Modeling of Complex Real-Time Control Systems [p. 498]
Cai, L.
Joint Power Management of Memory and Disk [p. 86]
Calazans, N.
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique [p. 502]
Calvano, J.
Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits [p. 174]
Campagnolo, R.
eMICAM: A New Generation of Active DNA Chip with in Situ Electrochemical Detection [p. 1338]
Canals, V.
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs [p. 206]
Carbonero, J.
Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach [p. 170]
Cardoso, J.
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs [p. 30]
Carro, L.
Noise Figure Evaluation Using Low Cost BIST [p. 158]
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-Based FPGAs [p. 1290]
Carta, S.
xpipes Lite: A Synthesis Oriented Design Library for Networks on Chips [p. 1188]
Carter, J.
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown [p. 300]
Casu, M.
A New System Design Methodology for Wire Pipelined SoC [p. 944]
Catthoor, F.
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware [p. 106]
Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives [p. 196]
A Complete Network-On-Chip Emulation Framework [p. 246]
Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules [p. 914]
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck [p. 946]
Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access [p. 1162]
Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code [p. 1310]
Ceng, J.
C Compiler Retargeting Based on Instruction Semantics Models [p. 1150]
Chakrabarti, P.
Mixing Global and Local Competition in Genetic Optimization Based Design Space Exploration of Analog Circuits [p. 1064]
Chakrabarty, K.
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores [p. 50]
Rapid Generation of Thermal-Safe Test Schedules [p. 840]
Hybrid BIST Based on Repeating Sequences and Cluster Analysis [p. 1142]
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration [p. 1196]
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips [p. 1202]
Chakraborty, S.
A New Task Model for Streaming Applications and its Schedulability Analysis [p. 486]
Chakravarty, S.
Implicit and Exact Path Delay Fault Grading in Sequential Circuits [p. 990]
Chandrakasan, A.
Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives [p. 196]
Chandrasekar, K.
Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation [p. 1002]
Chandy, A.
Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions [p. 984]
Chang, Y.-C.
JPEG, MPEG-4, and H.264 Codec IP Development [p. 1118]
Chao, H.
At-Speed Logic BIST for IP Cores [p. 860]
Chaput, J.-P.
TSUNAMI: An Integrated Timing-Driven Place and Route Research Platform [p. 920]
Chatterjee, A.
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits [p. 288]
Chen, C.C.-P.
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model [p. 952]
Chen, C.-L.
Integration, Verification and Layout of a Complex Multimedia SOC [p. 1116]
Chen, D.
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters [p. 279]
Chen, G.
A Constraint Network Based Approach to Memory Layout Optimization [p. 1156]
Chen, Gang
Defect Aware Test Patterns [p. 450]
Chen, Guangyu
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing [p. 1026]
Chen, Guilin
Locality-Aware Process Scheduling for Embedded MPSoCs [p. 870]
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing [p. 1026]
Chen, J.-J.
An Approximation Algorithm for Energy-Efficient Scheduling on a Chip Multiprocessor [p. 468]
Chen, K.
An Efficient Sequential SAT Solver with Improved Search Strategies [p. 1102]
Chen, L.-G.
JPEG, MPEG-4, and H.264 Codec IP Development [p. 1118]
Chen, T.
Systematic Analysis of Active Clock Deskewing Systems Using Control Theory [p. 820]
Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions [p. 984]
Chen, W.
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model [p. 952]
Chen, X.
Assertion-Based Design Exploration of DVS in Network Processor Architectures [p. 92]
Cheng, K.-T.
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver [p. 666]
An Efficient Sequential SAT Solver with Improved Search Strategies [p. 1102]
Cheon, B.
At-Speed Logic BIST for IP Cores [p. 860]
Cheong, E.
galsC: A Language for Event-Driven Embedded Systems [p. 1050]
Cheung, P.
Reconfigurable Elliptic Curve Cryptosystems on a Chip [p. 24]
Cheung, R.
Reconfigurable Elliptic Curve Cryptosystems on a Chip [p. 24]
Chiang, C.
Bright-Field AAPSM Conflict Detection and Correction [p. 908]
Chien, Y.-T.
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters [p. 279]
Cho, J.
At-Speed Logic BIST for IP Cores [p. 860]
Choi, K.
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization [p. 12]
Chopra, K.
Statistical Timing Based Optimization Using Gate Sizing [p. 400]
Chou, J.
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips [p. 1232]
Christie, P.
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [p. 36]
Chung, M.-K.
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation [p. 384]
Chureau, A.
The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application [p. 698]
Clément, H.
TSUNAMI: An Integrated Timing-Driven Place and Route Research Platform [p. 920]
Coburn, J.
Hardware Accelerated Power Estimation [p. 528]
Combaz, J.
Fine Grain QoS Control for Multimedia Application Software [p. 1038]
Cotofana, S.
Compositional Memory Systems for Multimedia Communicating Tasks [p. 932]
Cotterell, S.
System Synthesis for Networks of Programmable Blocks [p. 888]
Crand, S.
Systematic Figure of Merit Computation for the Design of Pipeline ADC [p. 277]
Crivellari, M.
Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking [p. 688]
Czendrodi, C.
Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits [p. 174]
Czutro, A.
Evolutionary Optimization in Code-Based Test Compression [p. 1124]

D

Daher, A. El
Activity Packing in FPGAs for Leakage Power Reduction [p. 212]
Daly, D.
Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives [p. 196]
Danelon, V.
Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach [p. 170]
Dasgupta, S.
Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures [p. 568]
Dasygenis, M.
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck [p. 946]
Datta, A.
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies [p. 926]
Dean, A.
Software Thread Integration and Synthesis for Real-Time Applications [p. 68]
Degalahal, V.
Compiler-Directed Instruction Duplication for Soft Error Detection [p. 1056]
Dehaene, W.
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [p. 36]
Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives [p. 196]
UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design [p. 716]
Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules [p. 914]
Delosme, J.-M.
Design Space Exploration for Dynamically Reconfigurable Architectures [p. 366]
Dershowitz, N.
Space-Efficient Bounded Model Checking [p. 686]
Dhillon, Y.
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits [p. 288]
Dielissen, J.
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification [p. 1182]
Ding, M.
A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling [p. 1088]
Diniz, P.
A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures [p. 6]
Diril, A.
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits [p. 288]
Doboli, A.
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption [p. 264]
Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip [p. 826]
Doerper, M.
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms [p. 876]
Donnay, S.
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance [p. 270]
Draxelmayr, D.
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [p. 36]
Dubreuil, H.
FPGA Architecture for Multi-Style Asynchronous Logic [p. 32]
Dubrova, E.
An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs [p. 406]
Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition [p. 430]
Structural Testing Based on Minimum Kernels [p. 1168]
Dueck, G.
Quantum Circuit Simplification Using Templates [p. 1208]
Dumont, S.
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement [p. 424]
Durinck, B.
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck [p. 946]
Dutt, N.
Functional Coverage Driven Test Generation for Validation of Pipelined Processors [p. 678]
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation [p. 786]
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations [p. 808]
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement [p. 1246]
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors [p. 1264]

E

Earlie, E.
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors [p. 1264]
Edwards, S.
The Challenges of Hardware Synthesis from C-like Languages [p. 66]
Eeckelaert, T.
Efficient Multiobjective Synthesis of Analog Circuits Using Hierarchical Pareto-Optimal Performances Hypersurfaces [p. 1070]
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming [p. 1082]
Eichenberger, S.
Memory Testing under Different Stress Conditions: An Industrial Evaluation [p. 438]
Eijndhoven, J. Van
Compositional Memory Systems for Multimedia Communicating Tasks [p. 932]
Eles, P.
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints [p. 514]
Design Optimization of Time- and Cost-Constrained Fault-Tolerant Distributed Embedded Systems [p. 864]
Elmasry, M.
Activity Packing in FPGAs for Leakage Power Reduction [p. 212]
Ensel, J.
Semiconductor Industry Disaggregation vs Reaggregation: Who will be the Shark? [p. 572]
Entrena-Arrontes, L.
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation [p. 308]
Ernst, R.
TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques [p. 312]
Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies [p. 480]
Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes [p. 938]
Escassut, R.
TSUNAMI: An Integrated Timing-Driven Place and Route Research Platform [p. 920]
Eversmann, B.
CMOS-Based Biosensor Arrays [p. 1222]

F

Fallah, F.
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors [p. 358]
Fang, H.-C.
JPEG, MPEG-4, and H.264 Codec IP Development [p. 1118]
Fatemi, H.
HEBS: Histogram Equalization for Backlight Scaling [p. 346]
Feinberg, E.
Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip [p. 826]
Ferdinand, C.
Verifying Safety-Critical Timing and Memory-Usage Properties of Embedded Software by Abstract Interpretation [p. 618]
Fernandez, J.-C.
Fine Grain QoS Control for Multimedia Application Software [p. 1038]
Ferrari, A.
Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development [p. 1044]
Fesquet, L.
FPGA Architecture for Multi-Style Asynchronous Logic [p. 32]
Flomenberg, J.
Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing [p. 126]
Flottes, M.
Mutation Sampling Technique for the Generation of Structural Test Data [p. 1022]
Fornaciari, W.
Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications [p. 748]
Forzan, C.
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis [p. 982]
Freund, U.
Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development [p. 1044]
Frey, A.
CMOS-Based Biosensor Arrays [p. 1222]
Fu, Z.
Considering Circuit Observability Don't Cares in CNF Satisfiability [p. 1108]
Fummi, F.
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation [p. 798]
Furusawa, T.
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction [p. 646]

G

Gadkari, A.
Automated Synthesis of Assertion Monitors Using Visual Specification [p. 390]
Gajski, D.
Functional Validation of System Level Static Scheduling [p. 542]
Defining an Enhanced RTL Semantics [p. 548]
Ganai, M.
Verification of Embedded Memory Systems Using Efficient Memory Modeling [p. 1096]
Gangwal, O.
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification [p. 1182]
Gangwar, A.
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures [p. 730]
García-Valderas, M.
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation [p. 308]
Garverick, S.
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories [p. 592]
Geilen, M.
Predictable Embedding of Large Data Structures in Multiprocessor Networks-On-Chip [p. 254]
Genko, N.
A Complete Network-On-Chip Emulation Framework [p. 246]
Germain, F.
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement [p. 424]
Ghanta, P.
Stochastic Power Grid Analysis Considering Process Variations [p. 964]
Ghenassia, F.
Is There a Market for SystemC Tools? [p. 950]
Ghosh, A.
LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks [p. 190]
Gianfagna, M.
Semiconductor Industry Disaggregation vs Reaggregation: Who will be the Shark? [p. 572]
Gielen, G.
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [p. 36]
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series [p. 120]
Efficient Multiobjective Synthesis of Analog Circuits Using Hierarchical Pareto-Optimal Performances Hypersurfaces [p. 1070]
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming [p. 1082]
Gill, B.
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories [p. 592]
Givargis, T.
LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks [p. 190]
Lightweight Multitasking Support for Embedded Systems Using the Phantom Serializing Compiler [p. 742]
Goel, S.
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips [p. 44]
Goor, A. Van De
Framework for Fault Analysis and Test Generation in DRAMs [p. 1020]
Goossens, K.
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification [p. 1182]
Gray, C.
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL [p. 152]
Groetker, T.
Is There a Market for SystemC Tools? [p. 950]
Gronthoud, G.
Memory Testing under Different Stress Conditions: An Industrial Evaluation [p. 438]
Guerrieri, R.
New Perspectives and Opportunities from the Wild West of Microelectronic Biochips [p. 1092]
Guo, Z.
Optimized Generation of Data-Path from C Codes for FPGAs [p. 112]
Gupta, A.
Verification of Embedded Memory Systems Using Efficient Memory Modeling [p. 1096]

H

Ha, D.
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing [p. 340]
Habibi, A.
Design for Verification of SystemC Transaction Level Models [p. 560]
Hakkinen, J.
IEEE 1149.4 Compatible ABMs for Basic RF Measurements [p. 172]
Hännikäinen, M.
UML 2.0 Profile for Embedded System Design [p. 710]
Hamann, A.
TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques [p. 312]
Hamdioui, S.
Framework for Fault Analysis and Test Generation in DRAMs [p. 1020]
Haneder, T.
CMOS-Based Biosensor Arrays [p. 1222]
Hanke, H.-C.
CMOS-Based Biosensor Arrays [p. 1222]
Hanna, Z.
Space-Efficient Bounded Model Checking [p. 686]
Hännikäinen, M.
UML 2.0 Profile for Embedded System Design [p. 710]
Hasegawa, T.
Integrating UML into SoC Design Process [p. 836]
Hashempour, H.
Evaluation of Error-Resilience for Reliable Compression of Test Data [p. 1284]
Hashimi, B. Al
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints [p. 514]
Hassan, H.
Activity Packing in FPGAs for Leakage Power Reduction [p. 212]
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC [p. 554]
Haubelt, C.
Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks [p. 894]
Haye, A. de la
Semiconductor Industry Disaggregation vs Reaggregation: Who will be the Shark? [p. 572]
Hayes, J.
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices [p. 282]
He, H.
Unified Modeling of Complex Real-Time Control Systems [p. 498]
He, L.
Scheduling of Soft Real-Time Systems for Context-Aware Applications [p. 318]
Buffer Insertion Considering Process Variation [p. 970]
Heckman, R.
Verifying Safety-Critical Timing and Memory-Usage Properties of Embedded Software by Abstract Interpretation [p. 618]
Heijligers, M.
Compositional Memory Systems for Multimedia Communicating Tasks [p. 932]
Heinecke, H.
Automotive System Design - Challenges and Potential [p. 656]
Henia, R.
Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies [p. 480]
Herkersdorf, A.
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization [p. 986]
Hermida, R.
A Complete Network-On-Chip Emulation Framework [p. 246]
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis [p. 1252]
Hessel, F.
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique [p. 502]
Hierlemannn, A.
Cantilever-Based Biosensors in CMOS Technology [p. 1340]
Hofmann, F.
CMOS-Based Biosensor Arrays [p. 1222]
Hohenauer, M.
C Compiler Retargeting Based on Instruction Semantics Models [p. 1150]
Holzapfl, B.
CMOS-Based Biosensor Arrays [p. 1222]
Hosseinabady, M.
Simultaneous Reduction of Dynamic and Static Power in Scan Structures [p. 846]
Houzet, D.
Systematic Figure of Merit Computation for the Design of Pipeline ADC [p. 277]
Hsiao, M.
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing [p. 340]
Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation [p. 1002]
Hsieh, H.
Assertion-Based Design Exploration of DVS in Network Processor Architectures [p. 92]
System Synthesis for Networks of Programmable Blocks [p. 888]
Hsu, P.
At-Speed Logic BIST for IP Cores [p. 860]
Hu, J.
Compiler-Directed Instruction Duplication for Soft Error Detection [p. 1056]
Hu, X.
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling [p. 634]
Hu, Y.
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model [p. 952]
Huang, Y.-W.
JPEG, MPEG-4, and H.264 Codec IP Development [p. 1118]
Hughes, G.
Striking a New Balance in the Nanometer Era: First-Time-Right and Time-To-Market Demands Versus Technology Challenges [p. 3]
Hung, A.
Symmetric Multiprocessing on Programmable Chips Made Easy [p. 240]
Hung, W.
Exact Synthesis of 3-qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory [p. 434]
Hung, W.-L.
Thermal-Aware Task Allocation and Scheduling for Embedded Systems [p. 898]
Huot, N.
FPGA Architecture for Multi-Style Asynchronous Logic [p. 32]
Huss, S.
A Dependability-Driven System-Level Design Approach for Embedded Systems [p. 372]

I

Ienne, P.
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement [p. 1246]
Illgen, T.
Process Oriented Software Quality Assurance - An Experience Report in Process Improvement - OEM Perspective [p. 536]
Imai, M.
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC [p. 554]
Iranli, A.
HEBS: Histogram Equalization for Backlight Scaling [p. 346]
Irwin, M.
Leakage-Aware Interconnect for On-Chip Network [p. 230]
Thermal-Aware Task Allocation and Scheduling for Embedded Systems [p. 898]
BB-GC: Basic-Block Level Garbage Collection [p. 1032]
Compiler-Directed Instruction Duplication for Soft Error Detection [p. 1056]
Ishihara, T.
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors [p. 358]
Issenin, I.
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations [p. 808]
Ivanov, A.
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs [p. 852]
Iyer, M.
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver [p. 666]
An Efficient Sequential SAT Solver with Improved Search Strategies [p. 1102]
Izosimov, V.
Design Optimization of Time- and Cost-Constrained Fault-Tolerant Distributed Embedded Systems [p. 864]

J

Jacobi, C.
Automatic Formal Verification of Fused-Multiply-Add FPUs [p. 1298]
Jaffari, J.
Simultaneous Reduction of Dynamic and Static Power in Scan Structures [p. 846]
Janssens, E.
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [p. 36]
Janssens, G.
Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code [p. 1310]
Jayabharathi, R.
Implicit and Exact Path Delay Fault Grading in Sequential Circuits [p. 990]
Jenei, S.
Estimating Scalable Common-Denominator Laplace-Domain MIMO Models in an Errors-in-Variables Framework [p. 1076]
Jenkner, M.
CMOS-Based Biosensor Arrays [p. 1222]
Jensen, E.
Energy-Efficient, Utility Accrual Real-Time Scheduling Under the Unimodal Arbitrary Arrival Model [p. 474]
Jha, N.
Secure Embedded Processing through Hardware-Assisted Run-time Monitoring [p. 178]
Jhumka, A.
A Dependability-Driven System-Level Design Approach for Embedded Systems [p. 372]
Jiang, R.
Efficient Solution of Language Equations Using Partitioned Representations [p. 418]
Jin, J.
Extended Control Flow Graph Based Performance Optimization Using Scratch-Pad Memory [p. 828]
Jung, J.
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization [p. 12]

K

Kahng, A.
Bright-Field AAPSM Conflict Detection and Correction [p. 908]
Kaibel, M.
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality [p. 56]
Kallakuri, S.
Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip [p. 826]
Kandemir, M.
Increasing Register File Immunity to Transient Errors [p. 586]
Nonuniform Banking for Reducing Memory Energy Consumption [p. 814]
Locality-Aware Process Scheduling for Embedded MPSoCs [p. 870]
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems [p. 882]
Thermal-Aware Task Allocation and Scheduling for Embedded Systems [p. 898]
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing [p. 1026]
BB-GC: Basic-Block Level Garbage Collection [p. 1032]
Compiler-Directed Instruction Duplication for Soft Error Detection [p. 1056]
A Constraint Network Based Approach to Memory Layout Optimization [p. 1156]
Reliability-Centric High-Level Synthesis [p. 1258]
Kang, K.
Statistical Timing Analysis Using Levelized Covariance Propagation [p. 764]
Kao, J.-C.
Energy-Aware Routing for E-Textile Applications [p. 184]
Karakoy, M.
A Constraint Network Based Approach to Memory Layout Optimization [p. 1156]
Karri, R.
Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths [p. 1214]
Kastensmidt, F.
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-Based FPGAs [p. 1290]
Katz, J.
Space-Efficient Bounded Model Checking [p. 686]
Kaul, H.
DVS for On-Chip Bus Designs Based on Timing Error Correction [p. 80]
Kavvadias, N.
Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications [p. 1060]
Kawabe, N.
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction [p. 646]
Kawarabayashi, M.
Is There a Market for SystemC Tools? [p. 950]
Keezer, D.
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL [p. 152]
Keitel-Schulz, D.
Challenges in Embedded Memory Design and Test [p. 722]
Kempf, T.
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms [p. 876]
Kennings, A.
Symmetric Multiprocessing on Programmable Chips Made Easy [p. 240]
An Improved Multi-Level Framework for Force-Directed Placement [p. 902]
Keshavarzi, A.
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs [p. 206]
Kgil, T.
Power-Performance Trade-offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage [p. 650]
Khan, J.
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms [p. 622]
Khatri, S.
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission [p. 1318]
Kheriji, R.
Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach [p. 170]
Kiemb, M.
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization [p. 12]
Kim, K.
Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths [p. 1214]
Kim, N.-S.
Power-Performance Trade-offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage [p. 650]
Kim, Y.
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization [p. 12]
Kirner, R.
Automatic Timing Model Generation by CFG Partitioning and Model Checking [p. 606]
Kirstein, K.-U.
Cantilever-Based Biosensors in CMOS Technology [p. 1340]
Kitahara, T.
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction [p. 646]
Klaus, S.
A Dependability-Driven System-Level Design Approach for Embedded Systems [p. 372]
Klingauf, W.
Systematic Transaction Level Modeling of Embedded Systems with SystemC [p. 566]
Kogel, T.
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms [p. 876]
Kolcu, I.
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems [p. 882]
Kong, J.
SoC in Nanoera: Challenges and Endless Possibility [p. 2]
Krishnaswamy, S.
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices [p. 282]
Kronlöf, K.
UML 2.0 Profile for Embedded System Design [p. 710]
Kruse, J.
Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes [p. 938]
Kukkala, P.
UML 2.0 Profile for Embedded System Design [p. 710]
Kumar, A.
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures [p. 730]
Kumar, S.
A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching [p. 770]
Kumar, V.
Implicit and Exact Path Delay Fault Grading in Sequential Circuits [p. 990]
Kuo, T.-W.
An Approximation Algorithm for Energy-Efficient Scheduling on a Chip Multiprocessor [p. 468]
Kyung, C.-M.
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation [p. 384]

L

Labunetz, A.
New Schemes for Self-Testing RAM [p. 858]
LaMeres, B.
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission [p. 1318]
Langenwalter, J.
Embedded Automotive System Development Process Steer-by-Wire System [p. 538]
Lavagno, L.
A Time Slice Based Scheduler Model for System Level Design [p. 378]
Leblebici, Y.
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit [p. 258]
Lee, E.
At-Speed Logic BIST for IP Cores [p. 860]
Lee, J.-G.
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation [p. 384]
Lee, S.-H.
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation [p. 384]
Lepley, T.
Fine Grain QoS Control for Multimedia Application Software [p. 1038]
Leung, L.-F.
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling [p. 634]
Leupers, R.
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms [p. 876]
C Compiler Retargeting Based on Instruction Semantics Models [p. 1150]
Li, Fei.
Scheduling of Soft Real-Time Systems for Context-Aware Applications [p. 318]
Li, Feihui
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing [p. 1026]
Compiler-Directed Instruction Duplication for Soft Error Detection [p. 1056]
Li, J.
A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching [p. 770]
Li, J.-F.
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories [p. 574]
Li, Lei
Hybrid BIST Based on Repeating Sequences and Cluster Analysis [p. 1142]
Li, Lin
Simultaneous Partitioning and Frequency Assignment for On-chip Bus Architectures [p. 218]
Li, M.
Q-DPM: An Efficient Model-Free Dynamic Power Management Technique [p. 526]
Li, P.
Specification Test Compaction for Analog Circuits and MEMS [p. 164]
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction [p. 958]
Li, S.-K.
A Faster Counterexample Minimization Algorithm Based on Refutation Analysis [p. 672]
Li, Y.
Cantilever-Based Biosensors in CMOS Technology [p. 1340]
Li, Z.
An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation [p. 752]
An O(bn2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types [p. 1324]
Lian, C.-J.
JPEG, MPEG-4, and H.264 Codec IP Development [p. 1118]
Liao, W.
Scheduling of Soft Real-Time Systems for Context-Aware Applications [p. 318]
Liau, E.
Computational Intelligence Characterization Method of Semiconductor Device [p. 456]
Lichtenberg, J.
Cantilever-Based Biosensors in CMOS Technology [p. 1340]
Lin, J.-Y.
Integration, Verification and Layout of a Complex Multimedia SOC [p. 1116]
Lin, T.
Modeling and Propagation of Noisy Waveforms in Static Timing Analysis [p. 776]
Lin, X.
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality [p. 56]
Lin, Y.-L.
Integration, Verification and Layout of a Complex Multimedia SOC [p. 1116]
Ling, M.
Extended Control Flow Graph Based Performance Optimization Using Scratch-Pad Memory [p. 828]
Link, G.
Hotspot Prevention through Runtime Reconfiguration in Network-On-Chip [p. 648]
Liu, F.
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores [p. 50]
Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing [p. 126]
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction [p. 958]
Liu, J.
galsC: A Language for Event-Driven Embedded Systems [p. 1050]
Liu, X.
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power [p. 1330]
Locht, L. De
Estimating Scalable Common-Denominator Laplace-Domain MIMO Models in an Errors-in-Variables Framework [p. 1076]
Loghi, M.
Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions [p. 508]
Tag Overflow Buffering: An Energy-Efficient Cache Architecture [p. 520]
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation [p. 798]
Lombardi, F.
On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories [p. 580]
Evaluation of Error-Resilience for Reliable Compression of Test Data [p. 1284]
López, J.
Model Reuse through Hardware Design Patterns [p. 324]
Lopez, L.
A New Embedded Measurement Structure for eDRAM Capacitor [p. 462]
López-Ongil, C.
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation [p. 308]
Lou, J.-H.
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters [p. 279]
Lousberg, M.
Memory Testing under Different Stress Conditions: An Industrial Evaluation [p. 438]
Lu, F.
An Efficient Sequential SAT Solver with Improved Search Strategies [p. 1102]
Lu, Y.-H.
Joint Power Management of Memory and Disk [p. 86]
Lubaszewski, M.
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture [p. 62]
Luk, W.
Reconfigurable Elliptic Curve Cryptosystems on a Chip [p. 24]
Lysecky, R.
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores Using Dynamic Hardware/Software Partitioning [p. 18]

M

Ma, G.-K.
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters [p. 279]
Macchiarulo, L.
A New System Design Methodology for Wire Pipelined SoC [p. 944]
Madsen, J.
A Network Traffic Generator Model for Fast Network-on-Chip Simulation [p. 780]
Maex, K.
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [p. 36]
Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules [p. 914]
Mahadevan, S.
A Network Traffic Generator Model for Fast Network-on-Chip Simulation [p. 780]
Mahapatra, R.
Lifetime Modeling of a Sensor Network [p. 202]
Mahmoodi, H.
A Novel Low-Overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application [p. 1136]
Majhi, A.
Memory Testing under Different Stress Conditions: An Industrial Evaluation [p. 438]
Majid, A.
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL [p. 152]
Makris, Y.
Concurrent Error Detection in Asynchronous Burst-Mode Controllers [p. 1272]
Malik, S.
Considering Circuit Observability Don't Cares in CNF Satisfiability [p. 1108]
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks [p. 1238]
Manaresi, N.
New Perspectives and Opportunities from the Wild West of Microelectronic Biochips [p. 1092]
Mangassarian, H.
On Statistical Timing Analysis with Inter and Intra-die Variations [p. 132]
Mangeruca, L.
Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development [p. 1044]
Mannion, R.
System Synthesis for Networks of Programmable Blocks [p. 888]
Manolios, P.
Refinement Maps for Efficient Verification of Processor Models [p. 1304]
Manquinho, V.
Effective Lower Bounding Techniques for Pseudo-Boolean Optimization [p. 660]
Mansouri, N.
Reliability-Centric High-Level Synthesis [p. 1258]
Marchal, P.
Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture [p. 736]
Marcon, C.
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique [p. 502]
Marculescu, D.
Energy Bounds for Fault-Tolerant Nanoscale Designs [p. 74]
Marculescu, R.
Energy-Aware Routing for E-Textile Applications [p. 184]
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach [p. 352]
Marescaux, T.
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles [p. 234]
Marinissen, E.
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips [p. 44]
Challenges in Embedded Memory Design and Test [p. 722]
Markov, I.
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices [p. 282]
Uniformly-Switching Logic for Cryptographic Hardware [p. 432]
Marques-Silva, J.
Effective Lower Bounding Techniques for Pseudo-Boolean Optimization [p. 660]
Martens, E.
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series [p. 120]
Martin, E.
Synchronization Processor Synthesis for Latency Insensitive Systems [p. 896]
Martin, P.
Design of a Virtual Component Neutral Network-on-Chip Transaction Layer [p. 336]
Martin, T.
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing [p. 340]
Martinelli, A.
Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition [p. 430]
Martini, S.
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation [p. 798]
Marwedel, P.
Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software [p. 600]
Maslov, D.
Uniformly-Switching Logic for Cryptographic Hardware [p. 432]
Quantum Circuit Simplification Using Templates [p. 1208]
Masson, C.
TSUNAMI: An Integrated Timing-Driven Place and Route Research Platform [p. 920]
Maté, J.-L.
Panel Session - Automotive System Architectures [p. 654]
Maurine, P.
Low Power Oriented CMOS Circuit Optimization Protocol [p. 640]
Mayer, A.
Is There a Market for SystemC Tools? [p. 950]
Mazumder, P.
EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation [p. 976]
McCausland, C.
Why Systems-on-Chip Needs More UML like a Hole in the Head [p. 834]
McConaghy, T.
Efficient Multiobjective Synthesis of Analog Circuits Using Hierarchical Pareto-Optimal Performances Hypersurfaces [p. 1070]
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming [p. 1082]
Medoro, G.
New Perspectives and Opportunities from the Wild West of Microelectronic Biochips [p. 1092]
Mellor, S.
Why Systems-on-Chip Needs More UML like a Hole in the Head [p. 834]
Memik, G.
Increasing Register File Immunity to Transient Errors [p. 586]
Mendías, J.
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis [p. 1252]
Mendias, J.
A Complete Network-On-Chip Emulation Framework [p. 246]
Meredith, M.
Is There a Market for SystemC Tools? [p. 950]
Mesman, B.
Predictable Embedding of Large Data Structures in Multiprocessor Networks-On-Chip [p. 254]
Mesquita, A.
Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits [p. 174]
Meyr, H.
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms [p. 876]
C Compiler Retargeting Based on Instruction Semantics Models [p. 1150]
Michel, X.
Low Power Oriented CMOS Circuit Optimization Protocol [p. 640]
Micheli, G. De
A Complete Network-On-Chip Emulation Framework [p. 246]
An Application-Specific Design Methodology for STbus Crossbar Generation [p. 1176]
xpipes Lite: A Synthesis Oriented Design Library for Networks on Chips [p. 1188]
Mignolet, J.-Y.
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles [p. 234]
Low Cost Task Migration Initiation in a Heterogeneous MP-SoC [p. 252]
Miller, D.
Quantum Circuit Simplification Using Templates [p. 1208]
Milligan, M.
Is There a Market for SystemC Tools? [p. 950]
Minami, F.
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction [p. 646]
Mir, S.
Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach [p. 170]
Miramond, B.
Design Space Exploration for Dynamically Reconfigurable Architectures [p. 366]
Miranda, M.
Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules [p. 914]
Mishchenko, A.
SAT-Based Complete Don't-Care Computation for Network Optimization [p. 412]
Efficient Solution of Language Equations Using Partitioned Representations [p. 418]
Mishra, P.
Functional Coverage Driven Test Generation for Validation of Pipelined Processors [p. 678]
Moilanen, M.
IEEE 1149.4 Compatible ABMs for Basic RF Measurements [p. 172]
Molina, M.
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis [p. 1252]
Molnos, A.
Compositional Memory Systems for Multimedia Communicating Tasks [p. 932]
Monchiero, M.
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip [p. 804]
Monguzzi, M.
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation [p. 798]
Moraes, F.
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture [p. 62]
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique [p. 502]
Moreno, E.
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture [p. 62]
Morgano, C.
Panel Session - Automotive System Architectures [p. 654]
Moya, F.
Model Reuse through Hardware Design Patterns [p. 324]
Mozos, D.
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware [p. 106]
Mudge, T.
DVS for On-Chip Bus Designs Based on Timing Error Correction [p. 80]
Power-Performance Trade-offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage [p. 650]
Mueller, G.
Framework for Fault Analysis and Test Generation in DRAMs [p. 1020]
Mueller, W.
A Model-Based Approach for Executable Specifications on Reconfigurable Hardware [p. 692]
Mukherjee, T.
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters [p. 279]
Mukhopadhyay, S.
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits [p. 224]
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies [p. 926]
Muller, P.
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit [p. 258]
Murali, S.
An Application-Specific Design Methodology for STbus Crossbar Generation [p. 1176]
Myers, D.
Design Refinement for Efficient Clustering of Objects in Embedded Systems [p. 718]

N

Nácul, A.
Lightweight Multitasking Support for Embedded Systems Using the Phantom Serializing Compiler [p. 742]
Nagata, M.
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits [p. 146]
Najjar, W.
Optimized Generation of Data-Path from C Codes for FPGAs [p. 112]
Nakata, T.
Integrating UML into SoC Design Process [p. 836]
Narayaynan, V.
Leakage-Aware Interconnect for On-Chip Network [p. 230]
Nassif, S.
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction [p. 958]
Navabi, Z.
Simultaneous Reduction of Dynamic and Static Power in Scan Structures [p. 846]
Nazarian, S.
Modeling and Propagation of Noisy Waveforms in Static Timing Analysis [p. 776]
Née, D.
A New Embedded Measurement Structure for eDRAM Capacitor [p. 462]
Negreiros, M.
Noise Figure Evaluation Using Low Cost BIST [p. 158]
Neiroukh, O.
Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques [p. 294]
Nicolaidis, M.
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories [p. 592]
Nicolau, A.
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors [p. 1264]
Nikolaidis, S.
Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications [p. 1060]
Nocco, S.
Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking [p. 688]
Noguchi, K.
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits [p. 146]
Nollet, V.
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles [p. 234]
Low Cost Task Migration Initiation in a Heterogeneous MP-SoC [p. 252]

O

Ogras, U.
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach [p. 352]
Oishi, R.
Integrating UML into SoC Design Process [p. 836]
Oliver, I.
Applying UML and MDA to Real Systems Design [p. 70]
Olsen, R.
A Network Traffic Generator Model for Fast Network-on-Chip Simulation [p. 780]
Ortmann, S.
Process Oriented Software Quality Assurance - An Experience Report in Process Improvement - OEM Perspective [p. 536]
Otálora, R. de
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization [p. 986]
Ottavi, M.
On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories [p. 580]
Ozev, S.
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores [p. 50]
Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing [p. 126]
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown [p. 300]
Ozturk, O.
Increasing Register File Immunity to Transient Errors [p. 586]
Nonuniform Banking for Reducing Memory Energy Consumption [p. 814]
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems [p. 882]
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing [p. 1026]
BB-GC: Basic-Block Level Garbage Collection [p. 1032]

P

Padmanabhan, U.
Nano-Sim: A Step Wise Equivalent Conductance Based Statistical Simulator for Nanotechnology Circuit Design [p. 758]
Palermo, G.
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip [p. 804]
Pamula, V.
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration [p. 1196]
Panainte, E.
Instruction Scheduling for Dynamic Hardware Configuration [p. 100]
Panda, P.
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures [p. 730]
Panda, R.
Stochastic Power Grid Analysis Considering Process Variations [p. 964]
Pandini, D.
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis [p. 982]
Papachristou, C.
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories [p. 592]
Papaefthymiou, M.
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power [p. 1330]
Park, C.
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization [p. 12]
Park, J.
At-Speed Logic BIST for IP Cores [p. 860]
Parthasarathy, G.
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver [p. 666]
An Efficient Sequential SAT Solver with Improved Search Strategies [p. 1102]
Paruthi, V.
Automatic Formal Verification of Fused-Multiply-Add FPUs [p. 1298]
Passerone, C.
A Time Slice Based Scheduler Model for System Level Design [p. 378]
Patra, A.
Mixing Global and Local Competition in Genetic Optimization Based Design Space Exploration of Analog Circuits [p. 1064]
Paul, B.
Statistical Timing Analysis Using Levelized Covariance Propagation [p. 764]
Paulus, C.
CMOS-Based Biosensor Arrays [p. 1222]
Pedram, M.
HEBS: Histogram Equalization for Backlight Scaling [p. 346]
Modeling and Propagation of Noisy Waveforms in Static Timing Analysis [p. 776]
Peh, L.-S.
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks [p. 1238]
Peng, Y.
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power [p. 1330]
Peng, Z.
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints [p. 514]
Design Optimization of Time- and Cost-Constrained Fault-Tolerant Distributed Embedded Systems [p. 864]
Perbellini, G.
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation [p. 798]
Perkowski, M.
Exact Synthesis of 3-qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory [p. 434]
Pestana, S. Gonzalez
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification [p. 1182]
Pileggi, L.
Specification Test Compaction for Analog Circuits and MEMS [p. 164]
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction [p. 958]
Pintelon, R.
Estimating Scalable Common-Denominator Laplace-Domain MIMO Models in an Errors-in-Variables Framework [p. 1076]
Plas, G. Van Der
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance [p. 270]
Poehl, F.
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality [p. 56]
Poggiali, A.
Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture [p. 736]
Poletti, F.
Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture [p. 736]
Polian, I.
Evolutionary Optimization in Code-Based Test Compression [p. 1124]
Pomante, L.
Reliable System Specification for Self-Checking Data-Paths [p. 1278]
Pomeranz, I.
Worst-Case and Average-Case Analysis of n-Detection Test Sets [p. 444]
Defect Aware Test Patterns [p. 450]
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits [p. 1008]
Poncino, M.
Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions [p. 508]
Tag Overflow Buffering: An Energy-Efficient Cache Architecture [p. 520]
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation [p. 798]
Pontarelli, S.
On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories [p. 580]
Pop, P.
Design Optimization of Time- and Cost-Constrained Fault-Tolerant Distributed Embedded Systems [p. 864]
Portal, J.
A New Embedded Measurement Structure for eDRAM Capacitor [p. 462]
Portela-García, M.
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation [p. 308]
Potkonjak, M.
Scheduling of Soft Real-Time Systems for Context-Aware Applications [p. 318]
Pozzi, L.
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement [p. 1246]
Press, R.
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality [p. 56]
Prince, B.
Challenges in Embedded Memory Design and Test [p. 722]
Pu, H.
Extended Control Flow Graph Based Performance Optimization Using Scratch-Pad Memory [p. 828]
Puschner, P.
Automatic Timing Model Generation by CFG Partitioning and Model Checking [p. 606]

Q

Qin, Y.
A Faster Counterexample Minimization Algorithm Based on Refutation Analysis [p. 672]
Quer, S.
Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking [p. 688]

R

Radulescu, A.
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification [p. 1182]
Raffo, L.
xpipes Lite: A Synthesis Oriented Design Library for Networks on Chips [p. 1188]
Raghunathan, A.
Secure Embedded Processing through Hardware-Assisted Run-time Monitoring [p. 178]
Hardware Accelerated Power Estimation [p. 528]
Rai, V.
Lifetime Modeling of a Sensor Network [p. 202]
Rajski, J.
Defect Aware Test Patterns [p. 450]
Ramesh, S.
Automated Synthesis of Assertion Monitors Using Visual Specification [p. 390]
Ravi, S.
Secure Embedded Processing through Hardware-Assisted Run-time Monitoring [p. 178]
Hardware Accelerated Power Estimation [p. 528]
Ravindran, B.
Energy-Efficient, Utility Accrual Real-Time Scheduling Under the Unimodal Arbitrary Arrival Model [p. 474]
Raychowdhury, A.
A Novel Low-Overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application [p. 1136]
Reddy, S.
Worst-Case and Average-Case Analysis of n-Detection Test Sets [p. 444]
Defect Aware Test Patterns [p. 450]
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits [p. 1008]
Reis, I.
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique [p. 502]
Renaudin, M.
FPGA Architecture for Multi-Style Asynchronous Logic [p. 32]
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement [p. 424]
Reorda, M. Sonza
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-Based FPGAs [p. 1290]
Resano, J.
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware [p. 106]
Reshadi, M.
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation [p. 786]
Rettberg, A.
A Model-Based Approach for Executable Specifications on Reconfigurable Hardware [p. 692]
Riccobene, E.
A SoC Design Methodology Involving a UML 2.0 Profile for SystemC_ [p. 704]
Rieder, B.
Automatic Timing Model Generation by CFG Partitioning and Model Checking [p. 606]
Riihimäki, J.
UML 2.0 Profile for Embedded System Design [p. 710]
Rijpkema, E.
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification [p. 1182]
Rincón, F.
Model Reuse through Hardware Design Patterns [p. 324]
Robach, C.
Mutation Sampling Technique for the Generation of Structural Test Data [p. 1022]
Rochange, C.
A Contribution to Branch Prediction Modeling in WCET Analysis [p. 612]
Rodrigues, R.
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs [p. 30]
Rolain, Y.
Estimating Scalable Common-Denominator Laplace-Domain MIMO Models in an Errors-in-Variables Framework [p. 1076]
Romani A.
New Perspectives and Opportunities from the Wild West of Microelectronic Biochips [p. 1092]
Rosales, M.
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs [p. 464]
Rosenstiel, W.
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs [p. 792]
Is There a Market for SystemC Tools? [p. 950]
Rosinger, P.
Rapid Generation of Thermal-Safe Test Schedules [p. 840]
Rosselló, J.
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs [p. 206]
Rosseló, J.
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs [p. 464]
Rosti, A.
A SoC Design Methodology Involving a UML 2.0 Profile for SystemC_ [p. 704]
Rouzeyre, B.
Mutation Sampling Technique for the Generation of Structural Test Data [p. 1022]
Roy, K.
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits [p. 224]
Statistical Timing Analysis Using Levelized Covariance Propagation [p. 764]
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies [p. 926]
A Novel Low-Overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application [p. 1136]
Ruiz-Sautua, R.
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis [p. 1252]
Ruparel, K.
Semiconductor Industry Disaggregation vs Reaggregation: Who will be the Shark? [p. 572]
Rutenbar, R.
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters [p. 279]

S

Sakallah, K.
Pueblo: A Modern Pseudo-Boolean SAT Solver [p. 684]
Sakanushi, K.
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC [p. 554]
Salice, F.
Reliable System Specification for Self-Checking Data-Paths [p. 1278]
Salsano, A.
On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories [p. 580]
Sami, M.
Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications [p. 748]
Sandireddy, R.
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits [p. 1014]
Sangiovanni-Vincentelli, A.
Integrated Electronics in the Car and the Design Chain Evolution or Revolution? [p. 532]
Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development [p. 1044]
Saputra, H.
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems [p. 882]
Savaria, Y.
The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application [p. 698]
Savioli, C.
Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits [p. 174]
Scandurra, P.
A SoC Design Methodology Involving a UML 2.0 Profile for SystemC_ [p. 704]
Schattkowsky, T.
A Model-Based Approach for Executable Specifications on Reconfigurable Hardware [p. 692]
UML 2.0 - Overview and Perspectives in SoC Design [p. 832]
Schaumont, P.
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip [p. 804]
Schiano, L.
On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories [p. 580]
Evaluation of Error-Resilience for Reliable Compression of Test Data [p. 1284]
Schienle, M.
CMOS-Based Biosensor Arrays [p. 1222]
Schindler-Bauer, P.
CMOS-Based Biosensor Arrays [p. 1222]
Schlenker, E.
Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development [p. 1044]
Schmitt-Landsiedel, D.
Computational Intelligence Characterization Method of Semiconductor Device [p. 456]
Schmitz, M.
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints [p. 514]
Schnerr, J.
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs [p. 792]
Scholivé, M.
Mutation Sampling Technique for the Generation of Structural Test Data [p. 1022]
Sciuto, D.
Reliable System Specification for Self-Checking Data-Paths [p. 1278]
Segura, J.
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs [p. 206]
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs [p. 464]
Sehgal, A.
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores [p. 50]
Seta, K.
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction [p. 646]
Shah, V.
A Time Slice Based Scheduler Model for System Level Design [p. 378]
Sharifi, S.
Simultaneous Reduction of Dynamic and Static Power in Scan Structures [p. 846]
Shashidhar, K.
Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code [p. 1310]
Sheini, H.
Pueblo: A Modern Pseudo-Boolean SAT Solver [p. 684]
Shen, S.
A Faster Counterexample Minimization Algorithm Based on Refutation Analysis [p. 672]
Shi, C.-J.
An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation [p. 752]
Shi, W.
An O(bn2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types [p. 1324]
Shrivastava, A.
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors [p. 1264]
Sifakis, J.
Fine Grain QoS Control for Multimedia Application Software [p. 1038]
Sinha, S.
Bright-Field AAPSM Conflict Detection and Correction [p. 908]
Slomka, F.
Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling [p. 492]
Soens, C.
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance [p. 270]
Somani, A.
Mixing Global and Local Competition in Genetic Optimization Based Design Space Exploration of Analog Circuits [p. 1064]
Song, W.
Cantilever-Based Biosensors in CMOS Technology [p. 1340]
Song, X.
Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques [p. 294]
Exact Synthesis of 3-qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory [p. 434]
Sorin, D.
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown [p. 300]
Soudris, D.
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck [p. 946]
Sparsø, J.
A Network Traffic Generator Model for Fast Network-on-Chip Simulation [p. 780]
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip [p. 1226]
Spengler, T.
Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes [p. 938]
Srinivasan, S.
Simultaneous Partitioning and Frequency Assignment for On-chip Bus Architectures [p. 218]
Refinement Maps for Efficient Verification of Processor Models [p. 1304]
Sroka, M.
TSUNAMI: An Integrated Timing-Driven Place and Route Research Platform [p. 920]
Stark, G.
Semiconductor Industry Disaggregation vs Reaggregation: Who will be the Shark? [p. 572]
Stechele, W.
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization [p. 986]
Stergiou, S.
xpipes Lite: A Synthesis Oriented Design Library for Networks on Chips [p. 1188]
Sterpone, L.
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-Based FPGAs [p. 1290]
Stitt, G.
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms [p. 396]
Storgaard, M.
A Network Traffic Generator Model for Fast Network-on-Chip Simulation [p. 780]
Streichert, T.
Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks [p. 894]
Stuijk, S.
Predictable Embedding of Large Data Structures in Multiprocessor Networks-On-Chip [p. 254]
Su, F.
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration [p. 1196]
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips [p. 1202]
Sukhwani, B.
Nano-Sim: A Step Wise Equivalent Conductance Based Statistical Simulator for Nanotechnology Circuit Design [p. 758]
Susin, A.
Noise Figure Evaluation Using Low Cost BIST [p. 158]
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique [p. 502]
Swarbrick, I.
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips [p. 1232]
Sylvester, D.
DVS for On-Chip Bus Designs Based on Timing Error Correction [p. 80]
Power-Performance Trade-offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage [p. 650]
Syri, P.
IEEE 1149.4 Compatible ABMs for Basic RF Measurements [p. 172]

T

Tahar, S.
A Public-Key Watermarking Technique for IP Designs [p. 330]
Design for Verification of SystemC Transaction Level Models [p. 560]
Taher, N.
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL [p. 152]
Tahoori, M.
An Accurate SER Estimation Method Based on Propagation Probability [p. 306]
Tajalli, A.
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit [p. 258]
Takeuchi, T.
OS Debugging Method Using a Lightweight Virtual Machine Monitor [p. 1058]
Takeuchi, Y.
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC [p. 554]
Talarico, C.
A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching [p. 770]
Tam, K.
Buffer Insertion Considering Process Variation [p. 970]
Tang, H.
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption [p. 264]
Defect Aware Test Patterns [p. 450]
Tartagni, M.
New Perspectives and Opportunities from the Wild West of Microelectronic Biochips [p. 1092]
Teich, J.
Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks [p. 894]
Teslenko, M.
An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs [p. 406]
Thadikaran, P.
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs [p. 996]
Thanailakis, A.
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck [p. 946]
Thewes, R.
CMOS-Based Biosensor Arrays [p. 1222]
Thiele, L.
A New Task Model for Streaming Applications and its Schedulability Analysis [p. 486]
Thomsen, C.
Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes [p. 938]
Tiri, K.
Design Method for Constant Power Consumption of Differential Logic Circuits [p. 628]
Tosun, S.
Reliability-Centric High-Level Synthesis [p. 1258]
Touba, N.
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination [p. 1130]
Tragoudas, S.
Implicit and Exact Path Delay Fault Grading in Sequential Circuits [p. 990]
Tsai, Y.-F.
Leakage-Aware Interconnect for On-Chip Network [p. 230]
Tseng, T.-W.
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories [p. 574]
Tsui, C.-Y.
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling [p. 634]
Tuncer, E.
Modeling and Propagation of Noisy Waveforms in Static Timing Analysis [p. 776]

V

Vahid, F.
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores Using Dynamic Hardware/Software Partitioning [p. 18]
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms [p. 396]
System Synthesis for Networks of Programmable Blocks [p. 888]
Vancura, C.
Cantilever-Based Biosensors in CMOS Technology [p. 1340]
Vanderperren, Y.
UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design [p. 716]
Vandersteen, G.
Estimating Scalable Common-Denominator Laplace-Domain MIMO Models in an Errors-in-Variables Framework [p. 1076]
Vanthournout, B.
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms [p. 876]
Vassiliadis, S.
Instruction Scheduling for Dynamic Hardware Configuration [p. 100]
Vemuri, R.
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis [p. 138]
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms [p. 622]
Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric [p. 922]
A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling [p. 1088]
Veneris, A.
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs [p. 996]
Venkataraman, S.
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs [p. 996]
Verbauwhede, I.
Design Method for Constant Power Consumption of Differential Logic Circuits [p. 628]
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip [p. 804]
Verghase, V.
Systematic Analysis of Active Clock Deskewing Systems Using Control Theory [p. 820]
Verkest, D.
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles [p. 234]
Low Cost Task Migration Initiation in a Heterogeneous MP-SoC [p. 252]
Verle, A.
Low Power Oriented CMOS Circuit Optimization Protocol [p. 640]
Viamontes, G.
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices [p. 282]
Vijaykrishnan, N.
Simultaneous Partitioning and Frequency Assignment for On-chip Bus Architectures [p. 218]
Hotspot Prevention through Runtime Reconfiguration in Network-On-Chip [p. 648]
Thermal-Aware Task Allocation and Scheduling for Embedded Systems [p. 898]
Compiler-Directed Instruction Duplication for Soft Error Detection [p. 1056]
Villa, O.
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip [p. 804]
Villa, T.
Efficient Solution of Language Equations Using Partitioned Representations [p. 418]
Vissers, K.
Optimized Generation of Data-Path from C Codes for FPGAs [p. 112]
Volden, T.
Cantilever-Based Biosensors in CMOS Technology [p. 1340]
Volling, T.
Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes [p. 938]
Vorwerk, K.
An Improved Multi-Level Framework for Force-Directed Placement [p. 902]
Vrudhula, S.
Stochastic Power Grid Analysis Considering Process Variations [p. 964]
Vucurevich, T.
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [p. 36]
Vulto, P.
New Perspectives and Opportunities from the Wild West of Microelectronic Biochips [p. 1092]

W

Wambacq, P.
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance [p. 270]
Wang, B.
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs [p. 852]
EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation [p. 976]
Wang, C.
Defect Aware Test Patterns [p. 450]
Wang, H.
Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules [p. 914]
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks [p. 1238]
Wang, J.
Nano-Sim: A Step Wise Equivalent Conductance Based Statistical Simulator for Nanotechnology Circuit Design [p. 758]
A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching [p. 770]
Stochastic Power Grid Analysis Considering Process Variations [p. 964]
Wang, L.-C.
An Efficient Sequential SAT Solver with Improved Search Strategies [p. 1102]
Wang, L.-T.
At-Speed Logic BIST for IP Cores [p. 860]
Wassung, D.
Semiconductor Industry Disaggregation vs Reaggregation: Who will be the Shark? [p. 572]
Watanabe, Y.
A Time Slice Based Scheduler Model for System Level Design [p. 378]
Weber, K.
Automatic Formal Verification of Fused-Multiply-Add FPUs [p. 1298]
Weber, W.-D.
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips [p. 1232]
Wehmeyer, L.
Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software [p. 600]
Wei, Y.
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption [p. 264]
Wen, X.
At-Speed Logic BIST for IP Cores [p. 860]
Wenzel, I.
Automatic Timing Model Generation by CFG Partitioning and Model Checking [p. 606]
Wey, C.-L.
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories [p. 574]
Windschiegl, A.
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization [p. 986]
Wingard, D.
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips [p. 1232]
Wolfe, J.
Why Systems-on-Chip Needs More UML like a Hole in the Head [p. 834]
Wolff, F.
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories [p. 592]
Wolff, H.-J.
Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development [p. 1044]
Wong, J.
Scheduling of Soft Real-Time Systems for Context-Aware Applications [p. 318]
Wu, C.-W.
SOC Testing Methodology and Practice [p. 1120]
Wu, H.
Energy-Efficient, Utility Accrual Real-Time Scheduling Under the Unimodal Arbitrary Arrival Model [p. 474]
Wu, K.
Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths [p. 1214]
Wu, S.
At-Speed Logic BIST for IP Cores [p. 860]
Wu, W.
Assertion-Based Design Exploration of DVS in Network Processor Architectures [p. 92]
Wu, X.
Q-DPM: An Efficient Model-Free Dynamic Power Management Technique [p. 526]
Wu, Y.
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs [p. 852]

X

Xie, Y.
Leakage-Aware Interconnect for On-Chip Network [p. 230]
Thermal-Aware Task Allocation and Scheduling for Embedded Systems [p. 898]
Reliability-Centric High-Level Synthesis [p. 1258]
Xiong, J.
Buffer Insertion Considering Process Variation [p. 970]
Xu, X.
Bright-Field AAPSM Conflict Detection and Correction [p. 908]

Y

Yakovlev, A.
Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures [p. 568]
Yan, X.
Q-DPM: An Efficient Model-Free Dynamic Power Management Technique [p. 526]
Yang, C.-Y.
An Approximation Algorithm for Energy-Efficient Scheduling on a Chip Multiprocessor [p. 468]
Yang, G.
Exact Synthesis of 3-qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory [p. 434]
Yang, J.
Assertion-Based Design Exploration of DVS in Network Processor Architectures [p. 92]
Yang, Y.-S.
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs [p. 996]
Yao, R.
Q-DPM: An Efficient Model-Free Dynamic Power Management Technique [p. 526]
Yardi, S.
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing [p. 340]
Yasaratne, D.
Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing [p. 126]
Yevtushenko, N.
Efficient Solution of Language Equations Using Partitioned Representations [p. 418]
Young, C.
Quantum Circuit Simplification Using Templates [p. 1208]
Young, P.
Systematic Analysis of Active Clock Deskewing Systems Using Control Theory [p. 820]
Yu, J.
Assertion-Based Design Exploration of DVS in Network Processor Architectures [p. 92]
Yu, Y.
Considering Circuit Observability Don't Cares in CNF Satisfiability [p. 1108]

Z

Zelikovsky, A.
Bright-Field AAPSM Conflict Detection and Correction [p. 908]
Zhang, L.
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model [p. 952]
Zhao, S.
Defining an Enhanced RTL Semantics [p. 548]
Zhong, Y.-F.
Unified Modeling of Complex Real-Time Control Systems [p. 498]
Zhu, Q.
Integrating UML into SoC Design Process [p. 836]
Zimmermann, M.
Cantilever-Based Biosensors in CMOS Technology [p. 1340]
Zorian, Y.
Semiconductor Industry Disaggregation vs Reaggregation: Who will be the Shark? [p. 572]
Challenges in Embedded Memory Design and Test [p. 722]
Zuber, P.
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization [p. 986]