DATE 2004 TABLE OF CONTENTS

DATE Executive Committee
Technical Program Chairs
Vendors Committee
DATE Sponsors Committee
Technical Program Committee
Reviewers
Foreword
Best Paper Awards
Tutorials
Master Courses
Call for Papers DATE 2005

Plenary : Keynote Session

Opportunities and Challenges in Building Silicon Products in 65nm and Beyond [p. 2]

G. Spirakis

1A: Architectural-Level Power Management

Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times [p. 4]

K. Choi, R. Soma, and M. Pedram

Hybrid Architectural Dynamic Thermal Management [p. 10]

K. Skadron

Value-Conscious Cache: Simple Technique for Reducing Cache Access Power [p. 16]

Y. Chang, C. Yang, and F. Lai

State-Preserving vs. Non-State-Preserving Leakage Control in Caches [p. 22]

D. Parikh, K. Sankaranarayanan, Y. Li, K. Skadron, Y. Zhang, and M. Stan

1B: Formal Verification Using Functional and Structural Information

Arithmetic Reasoning in DPLL-Based SAT Solving [p. 30]

M. Wedler, D. Stoffel, and W. Kunz

Enhanced Diameter Bounding via Structural Transformation [p. 36]

J. Baumgartner and A. Kuehlmann

Improved Symbolic Simulation by Dynamic Functional Space Partitioning [p. 42]

T. Feng, L. Wang, K. Cheng, and A. Lin

1C: Power, Timing and Diagnosis Constrained Testing

Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults [p. 50]

S. Padmanaban and S. Tragoudas

Level of Similarity: A Metric for Fault Collapsing [p. 56]

I. Pomeranz and S. Reddy

Design of Routing-Constrained Low Power Scan Chains [p. 62]

Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and A. Virazel

Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis [p. 68]

I. Pomeranz, S. Venkataraman, S. Reddy, and B. Seshadri

1D: Mixed-Signal Circuits and Systems

A 2.7V 350µW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs [p. 76]

A. Nagari and G. Nicollini

Digital Background Gain Error Correction in Pipeline ADCs [p. 82]

A. Ginés, E. Peralías, and A. Rueda

Digital Ground Bounce Reduction by Phase Modulation of the Clock [p. 88]

M. Badaroglu, G. Gielen, H. De Man, P. Wambacq, G. Van Der Plas, and S. Donnay

Pseudo-Random Sequence Based Tuning System for Continuous-Time Filters [p. 94]

A. Baschirotto, S. D'Amico, F. Corsi, C. Marzocca, and G. Matarrese

1E: Communication-Centric and Source-Level Optimisations for High-Level Synthesis

A Crosstalk Aware Interconnect with Variable Cycle Transmission [p. 102]

L. Li, N. Vijaykrishnan, M. Kandemir, and M. Irwin

Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip [p. 108]

N. Thepayasuwan and A. Doboli

Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow [p. 114]

S. Gupta, N. Dutt, A. Nicolau, and R. Gupta

1F: Panel Session: SystemC and System Verilog: Where do They Fit? Where are They Going?

SystemC and System Verilog: Where do They Fit? Where are they going? [p. 122]

2A: Low Power Systems and Architectures

Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus [p. 130]

S. Wong and C. Tsui

Hierarchical Adaptive Dynamic Power Management [p. 136]

Z. Ren, B. Krogh, and R. Marculescu

A Self-Tuning Cache Architecture for Embedded Systems [p. 142]

C. Zhang, F. Vahid, and R. Lysecky

Scheduling Reusable Instructions for Power Reduction [p. 148]

J. Hu, N. Vijaykrishnan, S. Kim, M. Kandemir, and M. Irwin

2B: Advanced Formal Verification Techniques

Using Counter Example Guided Abstraction Refinement to Find Complex Bugs [p. 156]

P. Bjesse and J. Kukula

Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor [p. 162]

G. Fey, D. Stoffel, H. Trylus, and K. Winkelmann

Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements [p. 168]

P. Manolios and S. Srinivasan

2C: New Algorithms for TPG

A Probabilistic Method for the Computation of Testability of RTL Constructs [p. 176]

J. Fernandes, M. Santos, A. Oliveira, and J. Teixeira

Graph-Based Functional Test Program Generation for Pipelined Processors [p. 182]

P. Mishra and N. Dutt

Automatic Generation of Validation Stimuli for Application-Specific Processors [p. 188]

O. Goloubeva, M. Sonza Reorda, and M. Violante

Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques [p. 194]

M. Dimopoulos and P. Linardis

2E: Optimisation of Memory Hierarchies

Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies [p. 202]

I. Issenin, N. Dutt, E. Brockmeyer, and M. Miranda

Automatic Tuning of Two-Level Caches to Embedded Applications [p. 208]

A. Gordon-Ross, F. Vahid, and N. Dutt

Low Static-Power Frequent-Value Data Caches [p. 214]

C. Zhang, J. Yang, and F. Vahid

Using a Victim Buffer in an Application-Specific Memory Hierarchy [p. 220]

C. Zhang and F. Vahid

2F: Hot Topic -- High Security Smartcards

High Security Smartcards [p. 228]

3A: New Directions in Low-Power Design

Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures Under Real-Time Constraints [p. 234]

J. Hu and R. Marculescu

A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations [p. 240]

T. Chen and J. Gregg

A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation [p. 246]

K. Tiri and I. Verbauwhede

Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling [p. 252]

W. Cheng, Y. Hou, and M. Pedram

3B: Advances in SAT

Managing Don't Cares in Boolean Satisfiability [p. 260]

S. Safarpour, A. Veneris, R. Drechsler, and J. Lee

Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors [p. 266]

M. Velev

A Novel SAT All-Solutions Solver for Efficient Preimage Computation [p. 272]

B. Li, M. Hsiao, and S. Sheng

3C: Analogue and High-Frequency Test

Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefits [p. 280]

G. Srinivasan, S. Bhattacharya, A. Chatterjee, and S. Cherubal

Random Jitter Extraction Technique in a Multi-Gigahertz Signal [p. 286]

C. Ong, D. Hong, K. Cheng, and L. Wang

Low Cost Analog Testing of RF Signal Paths [p. 292]

M. Negreiros, L. Carro, and A. Susin

A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications [p. 298]

D. Vázquez, G. Huertas, G. Leger, A. Rueda, and J. Huertas

3E: Energy Efficient Memory Usage

A Novel Implementation of Tile-Based Address Mapping [p. 306]

S. Hettiaratchi and P. Cheung

Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks [p. 312]

Z. Wang and X. Hu

Time-Energy Design Space Exploration for Multi-Layer Memory Architectures [p. 318]

R. Szymanek, K. Kuchcinski, and F. Catthoor

Breaking Instance-Independent Symmetries in Exact Graph Coloring [p. 324]

A. Ramani, F. Aloul, I. Markov, and K. Sakallah

3F: Hot Topic -- How Can System Level Design Solve the Interconnect Technology Scaling Problem?

How Can System Level Design Solve the Interconnect Technology Scaling Problem? [p. 332]

4A: System Level Design Methodology

System Design Using Kahn Process Networks: The Compaan/Laura Approach [p. 340]

E. Deprettere, B. Kienhuis, T. Stefanov, A. Turjan, and C. Zissulescu

Microarchitecture Development via Metropolis Successive Platform Refinement [p. 346]

D. Densmore, A. Sangiovanni-Vincentelli, and S. Rekhi

Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design [p. 352]

C. Shin, Y. Kim, E. Chung, K. Choi, J. Kong, and S. Eo

SoftContract: An Assertion-Based Software Development Process that Enables Design-by-Contract [p. 358]

J. Brunel, P. Giusto, M. di Natale, A. Ferrari, and L. Lavagno

A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors [p. 364]

D. Quinn, B. Lavigueur, G. Bois, and M. Aboulhamid

4B: System Level Modelling and Analysis

Refinement of Mixed-Signal Systems with Affine Arithmetic [p. 372]

C. Grimm, W. Heupke, and K. Waldschmidt

System-Level Performance Analysis in SystemC [p. 378]

H. Posadas, F. Herrera, P. Sánchez, E. Villar, and F. Blasco

Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks [p. 384]

M. Mousavi, P. Le Guernic, J. Talpin, S. Shukla, and T. Basten

Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures [p. 390]

V. D'Silva, S. Ramesh, and A. Sowmya

Aspects of Formal and Graphical Design of a Bus System [p. 396]

T. Seceleanu and T. Westerlund

4C: Advances in SoC Testing

Scan Power Minimization through Stimulus and Response Transformations [p. 404]

O. Sinanoglu and A. Orailoglu

Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally Asynchronous Locally-Synchronous SoC's [p. 410]

M. Heath, W. Burleson, and I. Harris

Wrapper Design for Testing IP Cores with Multiple Clock Domains [p. 416]

Q. Xu and N. Nicolici

Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures [p. 422]

A. Sehgal and K. Chakrabarty

An Arithmetic Structure for Test Data Horizontal Compression [p. 428]

M. Flottes, R. Poirier, and B. Rouzeyre

4E: New Issues in Analogue System- and Circuit-Level Performance Modelling

A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design [p. 436]

E. Martens and G. Gielen

Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques [p. 442]

L. Näthke, V. Burkhay, L. Hedrich, and E. Barke

Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines [p. 448]

T. Kiely and G. Gielen

Extended Subspace Identification of Improper Linear Systems [p. 454]

G. Vandersteen, D. Linten, R. Pintelon, and S. Donnay

Identification and Modeling of Nonlinear Dynamic Behavior in Analog Circuits [p. 460]

X. Huang and H. Mantooth

4F: Fabrics and Scheduling for Reconfigurable Computing

Exploring Logic Block Granularity for Regular Fabrics [p. 468]

A. Koorapaty, V. Kheterpal, P. Gopalakrishnan, M. Fu, and L. Pileggi

Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures [p. 474]

N. Bansal, S. Gupta, N. Dutt, A. Nicolau, and R. Gupta

A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning [p. 480]

R. Lysecky and F. Vahid

Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms [p. 486]

G. Chen, M. Kandemir, and U. Sezer

4G: Power Aware Design and Synthesis

Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization [p. 494]

D. Lee, H. Deogun, D. Blaauw, and D. Sylvester

A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks [p. 500]

P. Babighian, E. Macii, and L. Benini

Impact of Data Transformations on Memory Bank Locality [p. 506]

M. Kandemir

Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work [p. 512]

C. Kretzschmar, D. Müller, and A. Nieuwland

Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems [p. 518]

A. Andrei, M. Schmitz, P. Eles, Z. Peng, and B. Al-Hashimi

5A: System Level Design: Case Studies, Exploration and Optimisation

Dynamic Power Management Using Date Buffers [p. 526]

Y. Lu and L. Cai

Dynamic Memory Management Design Methodology for Reduced Memory. Footprint in Multimedia and Wireless Network Applications [p. 532]

D. Atienza, J. Mendias, S. Mamagkakis, D. Soudris, and F. Catthoor

High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study [p. 538]

H. Jang, M. Kang, K. Shim, M. Lee, K. Chae, and K. Lee

A SystemC-Based Verification Methodology for Complex Wireless Software IP [p. 544]

G. Post, P. Venkataraghavan, T. Ray, and D. Seetharaman

5B: Recent Advances in Digital Systems Simulation

A New Optimized Implementation of the SystemC Engine Using Acyclic Scheduling [p. 552]

D. Pérez, O. Temam, and G. Mouchard

Stimuli Generation with Late Binding of Values [p. 558]

A. Ziv

Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC [p. 564]

F. Fummi, S. Martini, G. Perbellini, and M. Poncino

Extraction of Schematic Array Models for Memory Circuits [p. 570]

S. Bose and A. Nandi

5C: On-Line Testing and Reliability for Nanometric Technology

Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors [p. 578]

A. Paschalis and D. Gizopoulos

Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA [p. 584]

M. Bellato, P. Bernardi, A. Candelori, M. Rebaudengo, M. Sonza Reorda, M. Violante, M. Ceschia, D. Bortolato, A. Paccagnella, and P. Zambolin

Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow [p. 590]

R. Leveugle and A. Ammari

On Concurrent Error Detection with Bounded Latency in FSMs [p. 596]

S. Almukhaizim, Y. Makris, and P. Drineas

5E: Parasitic-Aware Analogue Design

Fast, Layout-Inclusive Analog Circuit Synthesis Using Pre-Compiled Parasitic-Aware Symbolic Performance Models [p. 604]

M. Ranjan, A. Agarwal, H. Sampath, R. Vemuri, W. Verhaegen, and G. Gielen

Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis [p. 610]

R. Murgai, S. Reddy, T. Miyoshi, T Horie, and M. Tahoori

SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level [p. 616]

T. Brandtner and R. Weigel

Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming [p. 622]

Y. Zhan and S. Sapatnekar

5F: Hardware/Software System Design and Architecture Exploration

System Design for DSP Applications Using the MASIC Methodology [p. 630]

A. K. Deb, A. Jantsch, and J. Öberg

Flexible Software Protection Using Hardware/Software Codesign Techniques [p. 636]

J. Zambreno, A. Choudhary, R. Simha, and B. Narahari

Interactive Cosimulation with Partial Evaluation [p. 642]

P. Schaumont and I. Verbauwhede

Communication Analysis for System on Chip Design [p. 648]

A. Siebenborn, O. Bringmann, and W. Rosenstiel

5G: Hot Topic -- Extremely Low-Power Logic

Extremely Low-Power Logic [p. 656]

IP1: Interactive Presentations

Decomposition of Instruction Decoder for Low Power Design [p. 664]

W. Kuo, T. Hwang, and A. Wu

Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors [p. 666]

J. Laurent, N. Julien, E. Senn, and E. Martin

Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? [p. 668]

P. Basu, S. Das, P. Dasgupta, P. Chakrabarti, C. Mohan, and L. Fix

Functional Coverage Metric Generation from Temporal Event Relation Graph [p. 670]

Y. Kwon and C. Kyung

Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits [p. 672]

A. Efthymiou, D. Edwards, and C. Sotiriou

Automatic Synthesis and Simulation of Continuous-Time ΣΔ Modulators [p. 674]

H. Aboushady, L. de Lamarre, N. Beilleau, and M. Louërat

A Methodology for System-Level Analog Design Space Exploration [p. 676]

F. De Bernardinis and A. Sangiovanni-Vincentelli

Systematic Design for Optimization of High-Resolution Pipelined ADCs [p. 678]

R. Lotfi, M. Taherzadeh-Sani, and O. Shoaei

A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit [p. 680]

J. García, J. Montiel-Nelson, J. Sosa, and H. Navarro

Co-Processor Synthesis: A New Methodology for Embedded Software Acceleration [p. 682]

B. Hounsell and R. Taylor

Behavioural Bitwise Scheduling Based on Computational Effort Balancing [p. 684]

M. Molina, R. Ruiz-Sautua, J. Mendías, and R. Hermida

A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters [p. 686]

A. Nannarelli, A. Del Re, and M. Re

On Transfer Function and Power Consumption Transient Response [p. 688]

L. Cao

Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits [p. 690]

T. Raudvere, A. Singh, I. Sander, and A. Jantsch

Regression Simulation: Applying Path-Based Learning in Delay Test and Post-Silicon Validation [p. 692]

L. Wang

IP2: Interactive Presentations

A Game Theoretic Approach to Low Energy Wireless Video Streaming [p. 696]

A. Iranli, K. Choi, and M. Pedram

Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning [p. 698]

A. Ivaldi, A. Macii, E. Macii, and L. Benini

Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC [p. 700]

E. Macii, K. Patel, and M. Poncino

A Low Power Strategy for Future Mobile Terminals [p. 702]

M. Nikitovic and M. Brorsson

A 0.18 µm CMOS Implementation of On-Chip Analogue Test Signal Generation from Digital Test Patterns [p. 704]

L. Rolíndez, S. Mir, G. Prenat, and A. Bounceur

A Digital Test for First-Order ΣΔModulators [p. 706]

G. Leger and A. Rueda

Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis [p. 708]

S. Bhunia, A. Raychowdhury, and K. Roy

SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance [p. 710]

J. Chin and M. Nourani

STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores [p. 712]

M. Benabdenbi, F. Pêcheux, A. Greiner, M. Tuna and E. Viaud

Are Our Designs for Testability Features Fault Secure? [p. 714]

C. Metra, M. Omaña, and T. Mak

Test Compression and Hardware Decompression for Scan-Based SoCs [p. 716]

F. Wolff, C. Papachristou, and D. McIntyre

Concurrent Sizing, Vdd and V_th Assignment for Low-Power Design [p. 718]

A. Srivastava, D. Sylvester, and D. Blaauw

Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating [p. 720]

P. Babighian, E. Macii, and L. Benini

IP3: Interactive Presentations

An Asynchronous Synthesis Toolset Using Verilog [p. 724]

F. Burns, D. Shang, A. Koelmans, and A. Yakovlev

Organizing Libraries of DFG Patterns [p. 726]

G. Dittmann

Compositional Memory Systems for Data Intensive Applications [p. 728]

A. Molnos, M. Heijligers, J. Van Eijndhoven, and S. Cotofana

Scalar Metric for Temporal Locality and Estimation of Cache Performance [p. 730]

J. Alakarhu and J. Niittylahti

.NET Framework -- A Solution for the Next Generation Tools for System-Level Modeling and Simulation [p. 732]

J. Lapalme, E. Aboulhamid, G. Nicolescu, L. Charest, J. David, F. Boyer, and G. Bois

Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology [p. 734]

P. Viana, E. Barros, S. Rigo, R. Azevedo, and G. Araújo

Integrating the Synchronous Dataflow Model with UML [p. 736]

P. Green and S. Essa

Design and Behavioral Modeling Tools for Optical Network-On-Chip [p. 738]

M. Brière, L. Carrel, T. Michalke, F. Mieyeville, I. O'Connor, and F. Gaffiot

Hierarchical Modeling and Simulation of Large Analog Circuits [p. 740]

S. Tan, Z. Qi, and H. Li

Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS [p. 742]

P. Wilson, J. Ross, A. Brown, T. Kazmierski, and J. Baranowski

A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement [p. 744]

M. Handa and R. Vemuri

Enhancing Reliability of Operational Interconnections in FPGAs [p. 746]

A. Fit-Florea, M. Halas, and F. Kocan

Operating System Support for Interface Virtualization of Reconfigurable Coprocessors [p. 748]

M. Vuletic, L. Righetti, L. Pozzi, and P. Ienne

6A: Performances Analysis for MPSoC

Analyzing On-Chip Communication in a MPSoC Environment [p. 752]

F. Angiolini, D. Bertozzi, L. Benini, M. Loghi, and R. Zafalon

A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoCs [p. 758]

M. Grünewald, J. Niemann, M. Porrmann, and U. Rückert

Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach [p. 764]

S. Pestana, E. Rijpkema, A. Radulescu, K. Goossens, and O. Gangwal

A Case Study in Networks-on-Chip Design for Embedded Video [p. 770]

J. Xu, W. Wolf, T. Lv, J. Henkel, and S. Chakradhar

6B: Synthesis for Noise and Manufacturability

Exploiting Crosstalk to Speed up On-Chip Buses [p. 778]

C. Duan and S. Khatri

False-Noise Analysis for Domino Circuits [p. 784]

A. Glebov, S. Gavrilov, V. Zolotov, M. Becer, C. Oh, and R. Panda

Crosstalk Minimization in Logic Synthesis for PLA [p. 790]

Y. Liu, T. Hwang, and K. Wang

Synthesis for Manufacturability: A Sanity Check [p. 796]

A. Nardi and A. Sangiovanni-Vincentelli

6C: Support for BIST

Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit [p. 804]

M. Abas, D. Kinniment, and G. Russell

Impact of Test Point Insertion on Silicon Area and Timing during Layout [p. 810]

H. Vranken, H. Wunderlich, and F. Sapei

Designing Self Test Programs for Embedded DSP Cores [p. 816]

H. Rizk, C. Papachristou, and F. Wolff

6E: Modelling, Simulation and Optimisation in Power/Ground/Substrate

Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction [p. 824]

Z. Wang, J. Roychowdhury, and R. Murgai

Thermal and Power Integrity Based Power/Ground Networks Optimization [p. 830]

T. Wang, J. Tsai, and C. Chen

Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and Synthesis in Mixed-Signal ICs [p. 836]

H. Lan and R. Dutton

6F: Panel Session -- Chips of the Future: Soft, Crunchy or Hard?

Chips of the Future: Soft, Crunchy or Hard? [p. 844]

6G: Power-Aware Networks and Interfaces (Low Power Special Day)

Tuning In-Sensor Data Filtering to Reduce Energy Consumption in Wireless Sensor Networks [p. 852]

I. Kadayif and M. Kandemir

Power-Aware Network Swapping for Wireless Palmtop PCs [p. 858]

A. Acquaviva, E. Lattanzi, and A. Bogliolo

Power Aware Interface Synthesis for Bus-Based SoC Design [p. 864]

N. Liveris and P. Banerjee

Asynchronous Design by Conversion: Converting Synchronous Circuits into Asynchronous Ones [p. 870]

A. Branover, R. Kol, and R. Ginosar

7A: Networks on Chip Design

An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration [p. 878]

A. Radulescu, J. Dielissen, K. Goossens, E. Rijpkema, and P. Wielage

×pipesCompiler: A Tool for Instantiating Application Specific Networks-on-Chip [p. 884]

S. Murali, G. De Micheli, A. Jalabert, and L. Benini

Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip [p. 890]

M. Millberg, E. Nilsson, R. Thid, and A. Jantsch

Bandwidth-Constrained Mapping of Cores onto NoC Architectures [p. 896]

S. Murali and G. De Micheli

7B: Advances in Technology Mapping and Circuit Sizing

Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies [p. 904]

R. Zhang, P. Gupta, L. Zhong, and N. Jha

Fast Comparisons of Circuit Implementations [p. 910]

S. Karandikar and S. Sapatnekar

Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs [p. 916]

A. Tiwari and K. Tomko

MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis [p. 922]

M. Kumar, J. Bobba, and V. Kamakoti

7C: Panel Session -- Nanometer Design: What are the Requirements for Manufacturing Test?

Nanometer Design: What are the Requirements for Manufacturing Test? [p. 930]

7E: Issues in Interconnect Simulation and Model Order Reduction

Poor Man's TBR: A Simple Model Reduction Scheme [p. 938]

J. Phillips and L. Silveira

Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals [p. 944]

P. Feldmann

SCORE: Spice COmpatible Reluctance Extraction [p. 948]

R. Jiang and C. Chen

A Compact Propagation Delay Model for Deep-Submicron CMOS Technologies including Crosstalk [p. 954]

J. Rosselló and J. Segura

7F: Emerging Technologies: From Sensors to Qubits

A Framework for Battery-Aware Sensor Management [p. 962]

S. Dasika, S. Vrudhula, S. Chopra, and R. Srinivasan

Local Decisions and Triggering Mechanisms for Dynamic Fault Tolerance [p. 968]

P. Stanley-Marbell and D. Marculescu

An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology [p. 974]

P. Gupta and N. Jha

Smaller Two-Qubit Circuits for Quantum Communication and Computation [p. 980]

V. Shende, I. Markov, and S. Bullock

7G: Embedded Tutorial -- Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing

Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing [p. 988]

8A: Platform-Based Design and VC Reuse Methods

Measurement of IP Qualification Costs and Benefits [p. 996]

A. Vörg, W. Rosenstiel, and M. Radetzki

Architecture-Level Performance Estimation for IP-Based Embedded Systems [p. 1002]

K. Ueda, K. Sakanushi, Y. Takeuchi, and M. Imai

Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures [p. 1008]

M. Singh and M. Theobald

Platform Based on Open-Source Cores for Industrial Applications [p. 1014]

M. Bolado, J. Castillo, P. Huerta, H. Posadas, P. Sánchez, C. Sánchez, F. Blasco, and H. Fouren

MINCE: Matching INstructions with Combinational Equivalence for Extensible Processor [p. 1020]

N. Cheung, S. Parameswaran, J. Henkel, and J. Chan

8B: Real-Time Issues in Embedded Systems

Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications [p. 1028]

P. Pop, P. Eles, Z. Peng, V. Izosimov, M. Hellring, and O. Bridal

Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches [p. 1034]

Y. Tan and V. Mooney

Workload Characterization Model for Tasks with Variable Execution Demand [p. 1040]

A. Maxiaguine, S. Künzli, and L. Thiele

Context-Aware Performance Analysis for Efficient Embedded System Design [p. 1046]

M. Jersak, R. Henia, and R. Ernst

Compact Binaries with Code Compression in a Software Dynamic Translator [p. 1052]

S. Shogan and B. Childers

8C: Real-Life Defect Modelling and Detection

Pattern Selection for Testing of Deep Sub-Micron Timing Defects [p. 1060]

M. C. Chao, L. Wang, and K. Cheng

Balanced Excitation and its Effect on the Fortuitous Detection of Dynamic Defects [p. 1066]

J. Dworak, B. Cobb, J. Wingfield, and M. Mercer

Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis [p. 1072]

Y. Huang, W. Cheng, C. Hsieh, H. Tseng, A. Huang, and Y. Hung

A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuits [p. 1078]

C. Tirumurti, S. Kundu, S. Sur-Kolay, and Y. Chang

Soft Faults and the Importance of Stresses in Memory Testing [p. 1084]

Z. Al-Ars and A. van De Goor

8E: Optimisation in Physical Design

Wire Retiming for System-On-Chip by Fixpoint Computation [p. 1092]

C. Lin and H. Zhou

Boosting: Min-Cut Placement with Improved Signal Delay [p. 1098]

A. Kahng, S. Reda, and I. Markov

Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus [p. 1104]

L. Deng and M. Wong

A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk [p. 1110]

S. Gupta and S. Katkoori

Full-Chip Multilevel Routing for Power and Signal Integrity [p. 1116]

J. Xiong and L. He

8G: Hot Topic -- Platforms and Tools for Energy-Efficient Design of Multimedia Systems

Energy-Aware System Design for Wireless Multimedia [p. 1124]

9A: Communication Design for MPSoC

Unified Component Integration Flow for Multi-Processor SoC Design and Validation [p. 1132]

M. Dziri, W. Cesário, A. Jerraya, and F. Wagner

An Interconnect Channel Design Methodology for High Performance Integrated Circuits [p. 1138]

V. Chandra, A. Xu, H. Schmit, and L. Pileggi

Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach [p. 1144]

A. Bobrek, J. Pieper, J. Nelson, J. Paul, and D. Thomas

Supporting Cache Coherence in Heterogeneous Multiprocessor Systems [p. 1150]

T. Suh, D. Blough, and H. Lee

9B: Combining Static and Dynamic Software Optimisation

Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors [p. 1158]

I. Kadayif, M. Kandemir, and I. Kolcu

Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications [p. 1164]

C. Pinello, L. Carloni, and A. Sangiovanni-Vincentelli

Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems [p. 1170]

Y. Zhang and K. Chakrabarty

Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks [p. 1176]

L. Cortés, P. Eles, and Z. Peng

9C: Hot Topic -- The Status of the New IEEE Test Standards

Status of IEEE Testability Standards 1149.4, 1532 and 1149.6 [p. 1184]

S. Sunter, A. Osseiran, A. Cron, N. Jacobson, D. Bonnett, B. Eklow, C. Barnhart, and B. Bennetts

9E: Modelling and Estimation in Circuit Layout

Eliminating False Positives in Crosstalk Noise Analysis [p. 1192]

Y. Ran, M. Marek-Sadowska, A. Kondratyev, and Y. Watanabe

A New Approach to Timing Analysis Using Event Propagation and Temporal Logic [p. 1198]

A. Mondal, P. Chakrabarti, and C. Mandal

A New Effective Congestion Model in Floorplan Design [p. 1204]

Y. Hsieh and T. Hsieh

ULSI Interconnect Length Distribution Model Considering Core Utilization [p. 1210]

H. Nakashima, J. Inoue, K. Okada, and K. Masu

9G: Applications of Reconfigurability

Implementation of a UMTS Turbo-decoder on a Dynamically Reconfigurable Platform [p. 1218]

A. La Rosa, C. Passerone, F. Gregoretti, and L. Lavagno

Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study [p. 1224]

B. Mei, R. Lauwereins, S. Vernalde, and D. Verkest

Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays [p. 1230]

I. Ahmed, S. Baloch, A. Pai, T. Arslan, N. Aydin, S. Khawam, and F. Westall

Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience [p. 1236]

H. Krupnova

10A: Interconnect Modelling for MPSoC

Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing [p. 1244]

X. Zhu and S. Malik

A Power and Performance Model for Network-on-Chip Architectures [p. 1250]

N. Banerjee, P. Vellanki, and K. Chatha

A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms [p. 1256]

A. Wieferink, T. Kogel, R. Leupers, G. Ascheid, H. Meyr, G. Braun, and A. Nohl

10B: Embedded Software Generation and Optimisation

Cache-Aware Scratchpad Allocation Algorithm [p. 1264]

M. Verma, L. Wehmeyer, and P. Marwedel

Phase Coupled Code Generation for DSPs Using a Genetic Algorithm [p. 1270]

M. Lorenz and P. Marwedel

A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models [p. 1276]

M. Hohenauer, H. Scharwaechter, K. Karuri, O. Wahlen, T. Kogel, R. Leupers, G. Ascheid, H. Meyr, G. Braun, and H. van Someren

10C: Scan-Based Testing

Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression [p. 1284]

M. Tehranipour, M. Nourani, and K. Chakrabarty

CircularScan: A Scan Architecture for Test Cost Reduction [p. 1290]

B. Arslan and A. Orailoglu

Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets [p. 1296]

S. Wang, S. Chakradhar, and X. Liu

Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes [p. 1302]

A. Leininger, P. Muhmenthaler, and M. Goessel

10E: Novel Approaches to Analogue Simulation

Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation [p. 1310]

B. Wan and C. Shi

Direct Nonlinear Order Reduction with Variational Analysis [p. 1316]

L. Feng, X. Zeng, C. Chiang, D. Zhou, and Q. Fang

Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method [p. 1322]

X. Zhou, D. Zhou, J. Liu, R. Li, X. Zeng, and C. Chiang

Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits [p. 1327]

T. Mine, H. Kubota, A. Kamo, T. Watanabe, and H. Asai

10F: Embedded Tutorial -- System Verilog for VHDL Users

System Verilog for VHDL Users [p. 1334]

10G: Hot Topic -- Quo Vadis Multimedia? From Desktop Multimedia to Distributed Multimedia Systems

Distributed Multimedia System Design: A Holistic Perspective [p. 1342]

IP4: Interactive Presentations

Adaptive Prefetching for Multimedia Applications in Embedded Systems [p. 1350]

H. Sbeyti, S. Niar, and L. Eeckhout

Data Windows: A Data-Centric Approach for Query Execution in Memory-Resident Databases [p. 1352]

J. Pisharath, A. Choudhary, and M. Kandemir

High-Performance QuIDD-Based Simulation of Quantum Circuits [p. 1354]

G. Viamontes, I. Markov, and J. Hayes

An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation [p. 1356]

D. Reed, S. Levitan, J. Boles, J. Martinez, and D. Chiarulli

Fault Tolerance of Programmable Switch Blocks [p. 1358]

J. Huang, M. Tahoori, and F. Lombardi

A New Self-Checking Sum-Bit Duplicated Carry-Select Adder [p. 1360]

E. Sogomonyan, D. Marienfeld, V. Ocheretnij, and M. Gössel

A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation [p. 1362]

L. Elvira, F. Martorell, X. Aragonés, and J. González

Accurate Estimation of Parasitic Capacitances in Analog Circuits [p. 1364]

A. Agarwal, H. Sampath, V. Yelamanchili, and R. Vemuri

GRAAL -- A Development Framework for Embedded Graphics Accelerators [p. 1366]

D. Crisu, S. Cotofana, S. Vassiliadis, and P. Liuha

From Synchronous to Asynchronous: An Automatic Approach [p. 1368]

J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin, and C. Sotiriou

Enhancing Testability of System on Chips Using Network Management Protocols [p. 1370]

O. Laouamri and C. Aktouf

Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique [p. 1372]

M. Lampropoulos, B. Al-Hashimi, and P. Rosinger

Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors [p. 1374]

J. Aragon, D. Nicolaescu, A. Veidenbaum, and A. Badulescu

Dynamic Voltage and Cache Reconfiguration for Low Power [p. 1376]

A. Nacul and A. Givargis

IP5: Interactive Presentations

Overhead-free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models [p. 1380]

M. Goudarzi, S. Hessabi, and A. Mycroft

Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software [p. 1382]

S. Yoo, M. Youssef, A. Bouchhima, A. Jerraya, and M. Diaz-Nava

Synthesis of Reversible Logic [p. 1384]

A. Agrawal and N. Jha

A Unified Design Space for Regular Parallel Prefix Adders [p. 1386]

M. Ziegler and M. Stan

MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions [p. 1388]

A. Jabir and D. Pradhan

Issues in Implementing Latency Insensitive Protocols [p. 1390]

M. Casu and L. Macchiarulo

Model-Based Specification and Execution of Embedded Real-Time Systems [p. 1392]

T. Schattkowsky and W. Mueller

A Demonstration of Co-Design and Co-Verification in a Synchronous Language [p. 1394]

S. Singh

Profile Guided Management of Code Partitions for Embedded Systems [p. 1396]

S. Zhou, B. Childers, and N. Kumar

IP6: Interactive Presentations

Realizable Reduction for Electromagnetically Coupled RLMC Interconnects [p. 1400]

R. Jiang and C. Chen

Statistically Aware Buffer Planning [p. 1402]

G. Garcea, N. van der Meijs, and R. Otten

A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology [p. 1404]

S. Bernadini, J. Portal, and P. Masson

Power Supply Noise Monitor for Signal Integrity Faults [p. 1406]

J. Vázquez and J. de Gyvez

Testing of Quantum Dot Cellular Automata Based Designs [p. 1408]

M. Tahoori and F. Lombardi

Net and Pin Distribution for 3D Package Global Routing [p. 1410]

J. Minz, M. Pathak, and S. Lim

Placement Using a Localization Probability Model (LPM) [p. 1412]

M. Olbrich and E. Barke

CMOS Structures Suitable for Secured Hardware [p. 1414]

S. Guilley, P. Hoogvorst, Y. Mathieu, R. Pacalet, and J. Provost

Timing Correction and Optimization with Adaptive Delay Sequential Elements [p. 1416]

K. Rahimi, S. Bridges, and C. Diorio