DATE 2003 TABLE OF CONTENTS -- DESIGNERS' FORUM

Designers' Forum Committee
Embedded Software Forum Committee
Call for Papers DATE 2004

1D: Design Case Studies

Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level [p. 2]

H. Iwasaki, J. Naganuma, K. Nitta, K. Nakamura, T. Yoshitome, M. Ogura, Y. Nakajima, Y. Tashiro, T. Onishi, M. Ikeda, and M. Endo

HiBRID-SoC: A Multi-Core System-On-Chip Architecture for Multimedia Signal Processing Applications [p. 8]

H. Stolberg, M. Berekovic, L. Friebe, S. Moch, S. Flügel, X. Mao, M. Kulaczewski, H. Klußmann, and P. Pirsch

Efficient Field Processing Cores in an Innovative Protocol Processor System-On-Chip [p. 14]

G. Lykakis, N. Mouratidis, G. Konstantoulakis, K. Vlachos, N. Nikolaou, S. Perissakis, G. Sourdis, D. Pnevmatikatos, and D. Reisis

A Low Device Occupation IP to Implement Rijndael Algorithm [p. 20]

A. Panato, M. Barcelos, and R. Reis

Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0 [p. 26]

M. Caldari, M. Conti, L. Pieralisi, C. Turchetti, M. Coppola, and S. Curaba

System-Level Power Analysis Methodology Applied to the AMBA AHB Bus [p. 32]

M. Caldari, M. Conti, M. Coppola, P. Crippa, S. Orcioni, L. Pieralisi, and C. Turchetti

1E: Embedded Operating Systems for SoC (Embedded Software Forum)

Designing System-Level Software Solutions for Open OS's on 3g Wireless Handsets [p. 40]

S. Glaeson and E. Petit

Application Mapping to a Hardware Platform through Automated Code Generation Targeting a RTOS: A Design Case Study [p. 41]

M. Besana and M. Borgatti

Formal Methods for Integration of Automotive Software [p. 45]

M. Jersak, K. Richter, R. Ernst, J. Braam, Z. Jiang, and F. Wolf

Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect [p. 51]

F. Pétrot and P. Gomez

Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results [p. 57]

B. Nicolescu and R. Velazco

2D: Hot Topic: Network Processing Key Technologies and Architectural Components

Network Processing Challenges and an Experimental NPU Platform [p. 64]

P. Paulin, C. Pilkington, and E. Bensoudane

SPIN: A Scalable, Packet Switched, On-Chip Micro-Network [p. 70]

A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. Zeferino

NPSE: A High-Performance Network Packet Search Engine [p. 74]

N. Soni, N. Richardson, L. Huang, S. Rajgopal, and G. Vlantis

3D: SystemC Based Design

A Proposal for Transaction-Level Verification with Component Wrapper Language [p. 82]

K. Ara and K. Suzuki

Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard [p. 88]

F. Carbognani, C. Ip, P. Bates, A. Cochrane, and C. Lennard

A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification [p. 95]

A. Sayinta, G. Canverdi, A. Alshawa, M. Pauwels, and W. Dehaene

SystemC-VHDL Co-Simulation and Synthesis in the HW Domain [p. 101]

M. Bombana and F. Bruschi

IPSIM: SystemC 3.0 Enhancements for Communication Refinement [p. 106]

M. Coppola, S. Curaba, G. Maruccia, and M. Grammatikakis

Synthesis of Complex Control Structures from Behavioral SystemC Models [p. 112]

F. Bruschi and F. Ferrandi

3E: Embedded Software Design and Implementation (Embedded Software Forum)

Exploring SW Performance Using SoC Transaction-Level Modelling [p. 120]

I. Moussa, T. Grellier, and G. Nugyen

A Flexible Object-Oriented Software Architecture for Smart Wireless Communication Devices [p. 126]

M. Götze

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design [p. 132]

Y. Cho, G. Lee, K. Choi, S. Yoo, N. Zergainoh

Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device [p. 138]

S. Honda and H. Takada

Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 144]

H. Du, N. Tabrizi, N. Bagherzadeh, M. Sanchez-Elez, M. Fernandez, and M. Anido

Porting a Network Cryptographic Service to the RMC2000: A Case Study in Embedded Software Development [p. 150]

S. Jan, P. de Dios, and S. Edwards

4D: Design Exploration Methodologies

Fast Evaluation of Protocol Processor Architectures for IPv6 Routing [p. 158]

D. Truscan, S. Virtanen, and J. Lilius

A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems [p. 164]

S. Brini, D. Benjelloun, and F. Castanier

Transforming Structural Model to Runtime Model of Embedded Software with Real-Time Constraints [p. 170]

S. Kodase, S. Wang, and K. Shin

A Practical Approach for Bus Architecture Optimization at Transaction Level [p. 176]

O. Ogawa, K. Shinohara, Y. Watanabe, H. Niizuma, T. Sasaki, Y. Takai, S. de Noyer, and P. Chauvet

Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture [p. 182]

G. Palermo, C. Silvano, and V. Zaccaria

Estimation of Bus Performance for a Tuplespace in an Embedded Architecture [p. 188]

N. Drago, F. Fummi, M. Poncino, M. Monguzzi, and G. Perbellini

5D: Design Methodologies

Defining Cost Functions for Robust IC Design and Optimization [p. 196]

Á. Bürmen, J. Puhan, and T. Tuma

SoC Design and Test Considerations [p. 202]

M. Schrader and R. McConnell

A System to Validate and Certify Soft and Hard IP [p. 208]

B. Laurent and T. Karger

SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel [p. 214]

M. Caldari, M. Conti, P. Crippa, G. Marozzi, F. Di Gennaro, S. Orcioni, and C. Turchetti

Set Top Box SoC Design Methodology at STMicroelectronics [p. 220]

F. Remond and P. Bricaud

Verification of a Complex SoC: The PRO³ Case-Study [p. 224]

F. Andritsopoulos, G. Doumenis, C. Charopoulos, F. Karoubalis, Y. Mitsos, F. Petreas, I. Theologitou, S. Perissakis, and D. Reisis

6D: System Level Design Case Studies

System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive Domain [p. 232]

L. Mangeruca, A. Ferrari, A. Sangiovanni-Vincentelli, M. Pennese, and A. Pierantoni

HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder [p. 238]

M. Verderber, A. Zemva, and D. Lampret

Reconfigurable Signal Processing in Wireless Terminals [p. 244]

S. Di Matteo, S. Rossi, R. Bonitz, E. Schüler, P. Rao, and J. Helmschmidt

A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration [p. 250]

A. Baganne, I. Bennour, M. Elmarzougui, R. Gaiech, and E. Martin

Comparing Analytical Modeling with Simulation for Network Processors: A Case Study [p. 256]

C. Sauer, M. Gries, C. Kulkarni, and K. Keutzer

A Solution for Hardware Emulation of Non Volatile Memory Macrocells [p. 262]

A. Pirola

7D: Analogue and Mixed Signal Methodology Design

Bluetooth Transceiver Design with VHDL-AMS [p. 268]

R. Ahola, D. Wallner, and M. Sida

A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies [p. 274]

P. Daglio and C. Roma

Automatic Behavioural Model Calibration for Efficient PLL System Verification [p. 280]

A. Mounir, A. Mostafa, and M. Fikry

Verification of the RF Subsystem within Wireless LAN System Level Simulation [p. 286]

U. Knöchel, T. Markwirth, R. Kakerow, R. Atukula, and J. Hartung

A Top-Down Microsystems Design Methodology and Associated Challenges [p. 292]

M. McCorquodale, F. Gebara, K. Kraver, E. Marsman, R. Senger, and R. Brown

Synthesis of CMOS Analog Cells Using AMIGO [p. 297]

R. Iskander, M. Aly, M. Magdy, N. Hassan, N. Soliman, S. Moussa, and M. Dessouky