DATE 2003 AUTHOR INDEX -- DESIGNERS' FORUM

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [R] [S] [T] [V] [W] [Y] [Z]

A

Adriahantenaina, A.
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network [p. 70]
Ahola, R.
Bluetooth Transceiver Design with VHDL-AMS [p. 268]
Alshawa, A.
A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification [p. 95]
Aly, M.
Synthesis of CMOS Analog Cells Using AMIGO [p. 297]
Andritsopoulos, F.
Verification of a Complex SoC: The PRO3 Case-Study [p. 224]
Anido, M.
Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 144]
Ara, K.
A Proposal for Transaction-Level Verification with Component Wrapper Language [p. 82]
Atukula, R.
Verification of the RF Subsystem within Wireless LAN System Level Simulation [p. 286]

B

Baganne, A.
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration [p. 250]
Bagherzadeh, N.
Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 144]
Barcelos, M.
A Low Device Occupation IP to Implement Rijndael Algorithm [p. 20]
Bates, P.
Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard [p. 88]
Benjelloun, D.
A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems [p. 164]
Bennour, I.
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration [p. 250]
Bensoudane, E.
Network Processing Challenges and an Experimental NPU Platform [p. 64]
Berekovic, M.
HiBRID-SoC: A Multi-Core System-On-Chip Architecture for Multimedia Signal Processing Applications [p. 8]
Besana, M.
Application Mapping to a Hardware Platform through Automated Code Generation Targeting a RTOS: A Design Case Study [p. 41]
Bombana, M.
SystemC-VHDL Co-Simulation and Synthesis in the HW Domain [p. 101]
Bonitz, R.
Reconfigurable Signal Processing in Wireless Terminals [p. 244]
Borgatti, M.
Application Mapping to a Hardware Platform through Automated Code Generation Targeting a RTOS: A Design Case Study [p. 41]
Braam, J.
Formal Methods for Integration of Automotive Software [p. 45]
Bricaud, P.
Set Top Box SoC Design Methodology at STMicroelectronics [p. 220]
Brini, S.
A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems [p. 164]
Brown, R.
A Top-Down Microsystems Design Methodology and Associated Challenges [p. 292]
Bruschi, F.
SystemC-VHDL Co-Simulation and Synthesis in the HW Domain [p. 101]
Bruschi, F.
Synthesis of Complex Control Structures from Behavioral SystemC Models [p. 112]
Bürmen, Á.
Defining Cost Functions for Robust IC Design and Optimization [p. 196]

C

Caldari, M.
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0 [p. 26]
Caldari, M.
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus [p. 32]
Caldari, M.
SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel [p. 214]
Canverdi, G.
A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification [p. 95]
Carbognani, F.
Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard [p. 88]
Castanier, F.
A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems [p. 164]
Charlery, H.
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network [p. 70]
Charopoulos, C.
Verification of a Complex SoC: The PRO3 Case-Study [p. 224]
Chauvet, P.
A Practical Approach for Bus Architecture Optimization at Transaction Level [p. 176]
Cho, Y.
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design [p. 132]
Choi, K.
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design [p. 132]
Cochrane, A.
Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard [p. 88]
Conti, M.
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0 [p. 26]
Conti, M.
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus [p. 32]
Conti, M.
SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel [p. 214]
Coppola, M.
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0 [p. 26]
Coppola, M.
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus [p. 32]
Coppola, M.
IPSIM: SystemC 3.0 Enhancements for Communication Refinement [p. 106]
Crippa, P.
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus [p. 32]
Crippa, P.
SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel [p. 214]
Curaba, S.
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0 [p. 26]
Curaba, S.
IPSIM: SystemC 3.0 Enhancements for Communication Refinement [p. 106]

D

Daglio, P.
A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies [p. 274]
de Dios, P.
Porting a Network Cryptographic Service to the RMC2000: A Case Study in Embedded Software Development [p. 150]
de Noyer, S.
A Practical Approach for Bus Architecture Optimization at Transaction Level [p. 176]
Dehaene, W.
A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification [p. 95]
Dessouky, M.
Synthesis of CMOS Analog Cells Using AMIGO [p. 297]
Di Gennaro, F.
SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel [p. 214]
Di Matteo, S.
Reconfigurable Signal Processing in Wireless Terminals [p. 244]
Doumenis, G.
Verification of a Complex SoC: The PRO3 Case-Study [p. 224]
Drago, N.
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture [p. 188]
Du, H.
Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 144]

E

Edwards, S.
Porting a Network Cryptographic Service to the RMC2000: A Case Study in Embedded Software Development [p. 150]
Elmarzougui, M.
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration [p. 250]
Endo, M.
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level [p. 2]
Ernst, R.
Formal Methods for Integration of Automotive Software [p. 45]

F

Fernandez, M.
Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 144]
Ferrandi, F.
Synthesis of Complex Control Structures from Behavioral SystemC Models [p. 112]
Ferrari, A.
System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive Domain [p. 232]
Fikry, M.
Automatic Behavioural Model Calibration for Efficient PLL System Verification [p. 280]
Flügel, S.
HiBRID-SoC: A Multi-Core System-On-Chip Architecture for Multimedia Signal Processing Applications [p. 8]
Friebe, L.
HiBRID-SoC: A Multi-Core System-On-Chip Architecture for Multimedia Signal Processing Applications [p. 8]
Fummi, F.
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture [p. 188]

G

Gaiech, R.
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration [p. 250]
Gebara, F.
A Top-Down Microsystems Design Methodology and Associated Challenges [p. 292]
Glaeson, S.
Designing System-Level Software Solutions for Open OS's on 3g Wireless Handsets [p. 40]
Gomez, P.
Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect [p. 51]
Götze, M.
A Flexible Object-Oriented Software Architecture for Smart Wireless Communication Devices [p. 126]
Grammatikakis, M.
IPSIM: SystemC 3.0 Enhancements for Communication Refinement [p. 106]
Greiner, A.
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network [p. 70]
Grellier, T.
Exploring SW Performance Using SoC Transaction-Level Modelling [p. 120]
Gries, M.
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study [p. 256]

H

Hartung, J.
Verification of the RF Subsystem within Wireless LAN System Level Simulation [p. 286]
Hassan, N.
Synthesis of CMOS Analog Cells Using AMIGO [p. 297]
Helmschmidt, J.
Reconfigurable Signal Processing in Wireless Terminals [p. 244]
Honda, S.
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device [p. 138]
Huang, L.
NPSE: A High-Performance Network Packet Search Engine [p. 74]

I

Ikeda, M.
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level [p. 2]
Ip, C.
Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard [p. 88]
Iskander, R.
Synthesis of CMOS Analog Cells Using AMIGO [p. 297]
Iwasaki, H.
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level [p. 2]

J

Jan, S.
Porting a Network Cryptographic Service to the RMC2000: A Case Study in Embedded Software Development [p. 150]
Jersak, M.
Formal Methods for Integration of Automotive Software [p. 45]
Jiang, Z.
Formal Methods for Integration of Automotive Software [p. 45]

K

Kakerow, R.
Verification of the RF Subsystem within Wireless LAN System Level Simulation [p. 286]
Karger, T.
A System to Validate and Certify Soft and Hard IP [p. 208]
Karoubalis, F.
Verification of a Complex SoC: The PRO3 Case-Study [p. 224]
Keutzer, K.
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study [p. 256]
Klußmann, H.
HiBRID-SoC: A Multi-Core System-On-Chip Architecture for Multimedia Signal Processing Applications [p. 8]
Knöchel, U.
Verification of the RF Subsystem within Wireless LAN System Level Simulation [p. 286]
Kodase, S.
Transforming Structural Model to Runtime Model of Embedded Software with Real-Time Constraints [p. 170]
Konstantoulakis, G.
Efficient Field Processing Cores in an Innovative Protocol Processor System-On-Chip [p. 14]
Kraver, K.
A Top-Down Microsystems Design Methodology and Associated Challenges [p. 292]
Kulaczewski, M.
HiBRID-SoC: A Multi-Core System-On-Chip Architecture for Multimedia Signal Processing Applications [p. 8]
Kulkarni, C.
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study [p. 256]

L

Lampret, D.
HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder [p. 238]
Laurent, B.
A System to Validate and Certify Soft and Hard IP [p. 208]
Lee, G.
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design [p. 132]
Lennard, C.
Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard [p. 88]
Lilius, J.
Fast Evaluation of Protocol Processor Architectures for IPv6 Routing [p. 158]
Lykakis, G.
Efficient Field Processing Cores in an Innovative Protocol Processor System-On-Chip [p. 14]

M

Magdy, M.
Synthesis of CMOS Analog Cells Using AMIGO [p. 297]
Mangeruca, L.
System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive Domain [p. 232]
Mao, X.
HiBRID-SoC: A Multi-Core System-On-Chip Architecture for Multimedia Signal Processing Applications [p. 8]
Markwirth, T.
Verification of the RF Subsystem within Wireless LAN System Level Simulation [p. 286]
Marozzi, G.
SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel [p. 214]
Marsman, E.
A Top-Down Microsystems Design Methodology and Associated Challenges [p. 292]
Martin, E.
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration [p. 250]
Maruccia, G.
IPSIM: SystemC 3.0 Enhancements for Communication Refinement [p. 106]
McConnell, R.
SoC Design and Test Considerations [p. 202]
McCorquodale, M.
A Top-Down Microsystems Design Methodology and Associated Challenges [p. 292]
Mitsos, Y.
Verification of a Complex SoC: The PRO3 Case-Study [p. 224]
Moch, S.
HiBRID-SoC: A Multi-Core System-On-Chip Architecture for Multimedia Signal Processing Applications [p. 8]
Monguzzi, M.
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture [p. 188]
Mortiez, L.
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network [p. 70]
Mostafa, A.
Automatic Behavioural Model Calibration for Efficient PLL System Verification [p. 280]
Mounir, A.
Automatic Behavioural Model Calibration for Efficient PLL System Verification [p. 280]
Mouratidis, N.
Efficient Field Processing Cores in an Innovative Protocol Processor System-On-Chip [p. 14]
Moussa, I.
Exploring SW Performance Using SoC Transaction-Level Modelling [p. 120]
Moussa, S.
Synthesis of CMOS Analog Cells Using AMIGO [p. 297]

N

Naganuma, J.
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level [p. 2]
Nakajima, Y.
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level [p. 2]
Nakamura, K.
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level [p. 2]
Nicolescu, B.
Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results [p. 57]
Niizuma, H.
A Practical Approach for Bus Architecture Optimization at Transaction Level [p. 176]
Nikolaou, N.
Efficient Field Processing Cores in an Innovative Protocol Processor System-On-Chip [p. 14]
Nitta, K.
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level [p. 2]
Nugyen, G.
Exploring SW Performance Using SoC Transaction-Level Modelling [p. 120]

O

Ogawa, O.
A Practical Approach for Bus Architecture Optimization at Transaction Level [p. 176]
Ogura, M.
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level [p. 2]
Onishi, T.
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level [p. 2]
Orcioni, S.
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus [p. 32]
Orcioni, S.
SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel [p. 214]

P

Palermo, G.
Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture [p. 182]
Panato, A.
A Low Device Occupation IP to Implement Rijndael Algorithm [p. 20]
Paulin, P.
Network Processing Challenges and an Experimental NPU Platform [p. 64]
Pauwels, M.
A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification [p. 95]
Pennese, M.
System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive Domain [p. 232]
Perbellini, G.
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture [p. 188]
Perissakis, S.
Efficient Field Processing Cores in an Innovative Protocol Processor System-On-Chip [p. 14]
Perissakis, S.
Verification of a Complex SoC: The PRO3 Case-Study [p. 224]
Petit, E.
Designing System-Level Software Solutions for Open OS's on 3g Wireless Handsets [p. 40]
Petreas, F.
Verification of a Complex SoC: The PRO3 Case-Study [p. 224]
Pétrot, F.
Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect [p. 51]
Pieralisi, L.
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0 [p. 26]
Pieralisi, L.
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus [p. 32]
Pierantoni, A.
System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive Domain [p. 232]
Pilkington, C.
Network Processing Challenges and an Experimental NPU Platform [p. 64]
Pirola, A.
A Solution for Hardware Emulation of Non Volatile Memory Macrocells [p. 262]
Pirsch, P.
HiBRID-SoC: A Multi-Core System-On-Chip Architecture for Multimedia Signal Processing Applications [p. 8]
Pnevmatikatos, D.
Efficient Field Processing Cores in an Innovative Protocol Processor System-On-Chip [p. 14]
Poncino, M.
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture [p. 188]
Puhan, J.
Defining Cost Functions for Robust IC Design and Optimization [p. 196]

R

Rajgopal, S.
NPSE: A High-Performance Network Packet Search Engine [p. 74]
Rao, P.
Reconfigurable Signal Processing in Wireless Terminals [p. 244]
Reis, R.
A Low Device Occupation IP to Implement Rijndael Algorithm [p. 20]
Reisis, D.
Efficient Field Processing Cores in an Innovative Protocol Processor System-On-Chip [p. 14]
Reisis, D.
Verification of a Complex SoC: The PRO3 Case-Study [p. 224]
Remond, F.
Set Top Box SoC Design Methodology at STMicroelectronics [p. 220]
Richardson, N.
NPSE: A High-Performance Network Packet Search Engine [p. 74]
Richter, K.
Formal Methods for Integration of Automotive Software [p. 45]
Roma, C.
A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies [p. 274]
Rossi, S.
Reconfigurable Signal Processing in Wireless Terminals [p. 244]

S

Sanchez-Elez, M.
Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 144]
Sangiovanni-Vincentelli, A.
System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive Domain [p. 232]
Sasaki, T.
A Practical Approach for Bus Architecture Optimization at Transaction Level [p. 176]
Sauer, C.
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study [p. 256]
Sayinta, A.
A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification [p. 95]
Schrader, M.
SoC Design and Test Considerations [p. 202]
Schüler, E.
Reconfigurable Signal Processing in Wireless Terminals [p. 244]
Senger, R.
A Top-Down Microsystems Design Methodology and Associated Challenges [p. 292]
Shin, K.
Transforming Structural Model to Runtime Model of Embedded Software with Real-Time Constraints [p. 170]
Shinohara, K.
A Practical Approach for Bus Architecture Optimization at Transaction Level [p. 176]
Sida, M.
Bluetooth Transceiver Design with VHDL-AMS [p. 268]
Silvano, C.
Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture [p. 182]
Soliman, N.
Synthesis of CMOS Analog Cells Using AMIGO [p. 297]
Soni, N.
NPSE: A High-Performance Network Packet Search Engine [p. 74]
Sourdis, G.
Efficient Field Processing Cores in an Innovative Protocol Processor System-On-Chip [p. 14]
Stolberg, H.
HiBRID-SoC: A Multi-Core System-On-Chip Architecture for Multimedia Signal Processing Applications [p. 8]
Suzuki, K.
A Proposal for Transaction-Level Verification with Component Wrapper Language [p. 82]

T

Tabrizi, N.
Interactive Ray Tracing on Reconfigurable SIMD MorphoSys [p. 144]
Takada, H.
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device [p. 138]
Takai, Y.
A Practical Approach for Bus Architecture Optimization at Transaction Level [p. 176]
Tashiro, Y.
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level [p. 2]
Theologitou, I.
Verification of a Complex SoC: The PRO3 Case-Study [p. 224]
Truscan, D.
/A Fast Evaluation of Protocol Processor Architectures for IPv6 Routing [p. 158]
Tuma, T.
Defining Cost Functions for Robust IC Design and Optimization [p. 196]
Turchetti, C.
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0 [p. 26]
Turchetti, C.
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus [p. 32]
Turchetti, C.
SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel [p. 214] VV

V

Velazco, R.
Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results [p. 57]
Verderber, M.
HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder [p. 238]
Virtanen, S.
Fast Evaluation of Protocol Processor Architectures for IPv6 Routing [p. 158]
Vlachos, K.
Efficient Field Processing Cores in an Innovative Protocol Processor System-On-Chip [p. 14]
Vlantis, G.
NPSE: A High-Performance Network Packet Search Engine [p. 74]

W

Wallner, D.
Bluetooth Transceiver Design with VHDL-AMS [p. 268]
Wang, S.
Transforming Structural Model to Runtime Model of Embedded Software with Real-Time Constraints [p. 170]
Watanabe, Y.
A Practical Approach for Bus Architecture Optimization at Transaction Level [p. 176]
Wolf, F.
Formal Methods for Integration of Automotive Software [p. 45]

Y

Yoo, S.
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design [p. 132]
Yoshitome, T.
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level [p. 2]

Z

Zaccaria, V.
Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture [p. 182]
Zeferino, C.
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network [p. 70]
Zemva, A.
HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder [p. 238]
Zergainoh, N.
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design [p. 132]