DATE 2003 TABLE OF CONTENTS

DATE Executive Committee
Technical Program Chairs
Vendors Committee
DATE Sponsor Committee
Technical Program Committee
Reviewers
Welcome to DATE 2003
Best Paper Awards
Tutorials
Master Courses
Call for Papers DATE 2004

Plenary: Keynote Session

IC Design Challenges for Ambient Intelligence [p. 2]

E. Aarts and R. Roovers

Semiconductor Challenges [p. 8]

A. Cuomo

1A: Hot Topic: Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts

Panel Statement [p. 10]

1B: Energy-Efficient Memory Systems

Improving the Efficiency of Memory Partitioning by Address Clustering [p. 18]

A. Macii, E. Macii, and M. Poncino

A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors [p. 24]

A. Macii, E. Macii, F. Crudo, and R. Zafalon

Power Efficiency through Application-Specific Instruction Memory Transformations [p. 30]

P. Petrov and A. Orailoglu

Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures [p. 36]

M. Sánchez-Élez, M. Fernández, M. Anido, H. Du, R. Hermida, and N. Bagherzadeh

1C: Embedded Tutorial: Circuit, Platform Design and Test Challenges in Technologies Beyond 90nm

Panel Statement [p. 44]

1F: Uncertainty

Global Wire Bus Configuration with Minimum Delay Uncertainty [p. 50]

L. Huang, H. Chen, and D. Wong

Timing Verification with Crosstalk for Transparently Latched Circuits [p. 56]

H. Zhou

Statistical Timing Analysis Using Bounds [p. 62]

A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula

Reduced Delay Uncertainty in High Performance Clock Distribution Networks [p. 68]

D. Velenis, E. Friedman, and M. Papaefthymiou

2A: Hot Topic: Scaling into Ambient Intelligence

Panel Statement [p. 76]

2B: Power-Aware Design and Synthesis

Masking the Energy Behavior of DES Encryption [p. 84]

H. Saputra, S. Vijaykrishnan, M. Kandemir, M. Irwin, R. Brooks, S. Kim, and W. Zhang

Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems [p. 90]

D. Wu, B. Al-Hashimi, and P. Eles

Synthesis of Application-Specific Highly Efficient Multi-Mode Systems for Low-Power Applications [p. 96]

L. Chiou, S. Bhunia, and K. Roy

2C: Test Data Compression

Virtual Compression through Test Vector Stitching for Scan Based Design [p. 104]

W. Rao and A. Orailoglu

Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture [p. 110]

N. Oh, R. Kapur, T. Williams, and J. Sproch

A Technique for High Ratio LZW Compression [p. 116]

M. Knieser, D. Weyer, R. McIntyre, F. Wolff, and C. Papachristou

Fast Computation of Data Correlation Using BDDs [p. 122]

Z. Zeng, Q. Zhang, I. Harris, and M. Ciesielski

2E: Operating System Abstraction and Targeting (Embedded Software Forum)

RTOS Modeling for System Level Design [p. 130]

A. Gerstlauer, H. Yu, and D. Gajski

Modeling and Integration of Peripheral Devices in Embedded Systems [p. 136]

S. Wang, S. Malik, and R. Bergamaschi

Systematic Embedded Software Generation from SystemC [p. 142]

F. Herrera, H. Posadas, P. Sánchez, and E. Villar

2F: Analysis of Jitter and Noise for Analogue Systems and SD Modelling and Simulation

Noise Macromodel for Radio Frequency Integrated Circuits [p. 150]

Y. Xu, X. Li, P. Li, and L. Pileggi

Approximation Approach for Timing Jitter Characterization in Circuit Simulators [p. 156]

M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov, K. Gullapalli, and B. Mulvaney

A Model of Computation for Continuous-Time Delta-Sigma Modulators [p. 162]

E. Martens and G. Gielen

Behavioural Modelling and Simulation of Delta-Sigma Modulators Using Hardware Description Languages [p. 168]

R. Castro-López, F. Fernández, F. Medeiro, and A. Rodríguez-Vázquez

3A: Hot Topic: Securing Mobile Appliance: New Challenges for the System Designer

Panel Statement [p. 176]

3B: Scheduling and Analysis of Embedded Systems

Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems [p. 184]

P. Pop, P. Eles, and Z. Peng

A General Framework for Analysing System Properties in Platform-Based Embedded System Designs [p. 190]

S. Chakraborty, S. Kuenzli, and L. Thiele

Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration [p. 196]

G. Logothetis and K. Schneider

Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures [p. 204]

B. Rinner, M. Schmid, and R. Weiss

3C: Recent Advances in DFT and BIST

DFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers [p. 212]

M. Nummer and M. Sachdev

Extending JTAG for Testing Signal Integrity in SoCs [p. 218]

N. Ahmed, M. Tehranipour, and M. Nourani

EBIST: A Novel Test Generator with Built-In Fault Detection Capability [p. 224]

D. Pradhan, C. Liu, and K. Chakraborty

A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-On-Chip Fault Diagnosis [p. 230]

C. Liu and K. Chakrabarty

3F: Analogue and RF Modelling, Simulation and Optimisation

Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors [p. 238]

P. Vanassche, G. Gielen, and W. Sansen

A New Simulation Technique for Periodic Small-Signal Analysis [p. 244]

M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov, and J. Mulvaney

Generalized Posynomial Performance Modeling [p. 250]

T. Eeckelaert, W. Daems, G. Gielen, and W. Sansen

Holmes: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits [p. 256]

B. De Smedt and G. Gielen

4A: Architectural Level Synthesis

High-Level Allocation to Minimize Internal Hardware Wastage [p. 264]

M. Molina, J. Mendías, and R. Hermida

Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs [p. 270]

S. Gupta, N. Dutt, R. Gupta, and A. Nicolau

Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units [p. 276]

E. Kim, H. Saito, H. Nakamura, T. Nanya, J. Lee, and D. Lee

Automated Bus Generation for Multiprocessor SoC Design [p. 282]

K. Ryu and V. Mooney III

4B: Scheduling in Reconfigurable Computing

Online Scheduling for Block-Partitioned Reconfigurable Devices [p. 290]

H. Walder and M. Platzner

Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling [p. 296]

B. Mei, H. De Man, R. Lauwereins, S. Vernalde, and D. Verkest

Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems [p. 302]

S. Lange and U. Kebschull

4C: Delay Testing and Diagnosis

A Method of Test Generation for Path Delay Faults Using Stuck-At Fault Test Generation Algorithms [p. 310]

S. Ohtake, K. Ohtani, and H. Fujiwara

A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification [p. 316]

M. Syal and M. Hsiao

Non-Enumerative Path Delay Fault Diagnosis [p. 322]

S. Padmanaban and S. Tragoudas

Delay Defect Diagnosis Based Upon Statistical Timing Models -- The First Step [p. 328]

A. Krstic, L. Wang, K. Cheng, J. Liou, and M. Abadir

4E: Embedded Tutorial: Embedded Operating Systems for SoC (Embedded Software Forum)

Introduction to Hardware Abstraction Layers for SoC [p. 336]

S. Yoo and A. Jerraya

Hardware/Software Partitioning of Operating Systems [p. 338]

V. Mooney III

Embedded Software in Digital AM-FM Chipset [p. 340]

M. Sarlotte, B. Candaele, J. Quevremont, and D. Merel

4F: Networks-on-Chip

Packetized On-Chip Interconnect Communication Analysis for MPSoC [p. 344]

T. Ye, G. De Micheli, and L. Benini

Trade Offs in the Design of a Router with both Guaranteed and Best-Effort Services for Networks On Chip [p. 350]

E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander

Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors [p. 356]

F. Gilbert, M. Thul, and N. Wehn

5A: System Level Modelling

Development and Application of Design Transformations in ForSyDe [p. 364]

I. Sander, A. Jantsch, and Z. Lu

System Level Specification in Lava [p. 370]

S. Singh

Formal Semantics of Synchronous SystemC [p. 376]

A. Salem

Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated [p. 382]

F. Doucet, R. Gupta, and S. Shukla

SystemC-AMS Requirements, Design Objectives and Rationale [p. 388]

A. Vachoux, C. Grimm, and K. Einwich

5B: Hot Topic: Runtime Reconfigurable Systems on Chip -- An Industry Perspective

Parallel Processing Architectures for Reconfigurable Systems [p. 396]

K. Vissers

Different Approaches to Add Reconfigurability in a SoC Architecture [p. 398]

B. Gupta and M. Borgatti

A Lightweight Approach for Embedded Reconfiguration of FPGAs [p. 399]

B. Blodget, S. McMillan, and P. Lysaght

5C: Hot Topic: Creating Value Through Test

Panel Statement [p. 402]

5E: Software Optimisation for Embedded Systems (Embedded Software Forum)

Control Flow Driven Splitting of Loop Nests at the Source Code Level [p. 410]

H. Falk and P. Marwedel

Data Space Oriented Scheduling in Embedded Systems [p. 416]

M. Kandemir, G. Chen, W. Zhang, and I. Kolcu

Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling [p. 422]

S. Pillai and M. Jacome

An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling [p. 428]

A. Lomeña, M. López-Vallejo, Y. Watanabe, and A. Kondratyev

5F: Global Approaches to Layout Synthesis

Time Budgeting in a Wireplanning Context [p. 436]

J. Westra, R. Otten, D. Jongeneel, and C. Visweswariah

Interconnect Planning with Local Area Constrained Retiming [p. 442]

R. Lu and C. Koh

A Novel Metric for Interconnect Architecture Performance [p. 448]

P. Dasgupta, A. Kahng, and S. Muddu

6A: Platform Design and IP Reuse Methods

Specification of Non-Functional Intellectual Property Components [p. 456]

J. Zhu and W. Mong

Profile-Driven Selective Code Compression [p. 462]

Y. Xie, W. Wolf, and H. Lekatsas

Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver [p. 468]

C. Pan, N. Bagherzadeh, A. Kamalizad, and A. Koohi

6B: Panel: Reconfigurable Computing -- Different Perspectives

Panel Statement [p. 476]

6C: Analogue and Defect-Oriented Testing

RF-BIST: Loopback Spectral Signature Analysis [p. 478]

D. Lupea, U. Pursche, and H. Jentschel

Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation [p. 484]

Z. Al-Ars, A. van de Goor, J. Braun, and D. Richter

On Modeling Cross-Talk Faults [p. 490]

S. Zachariah, Y. Chang, S. Kundu, and C. Tirumurti

Techniques for Automatic on Chip Closed Loop Transfer Function Monitoring for Embedded Charge Pump Phase Locked Loops [p. 496]

M. Burbidge, A. Richardson, and J. Tijou

6E: Energy Aware Software Techniques (Embedded Software Forum)

Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and General Purpose Software Applications [p. 504]

V. Rapaka and D. Marculescu

Runtime Code Parallelization for On-Chip Multiprocessors [p. 510]

M. Kandemir, W. Zhang, and M. Karakoy

SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms [p. 516]

P. Marchal, F. Catthoor, D. Bruni, L. Benini, J. Gomez, L. Piñuel, and H. Corporaal

6F: Interconnect Modelling and Signal Integrity

Modeling and Evaluation of Substrate Noise Induced by Interconnects [p. 524]

F. Martorell, D. Mateo, and X. Aragonès

Model-Order Reduction Based on PRONY's Method [p. 530]

M. Mansour and A. Mehrotra

Combined FDTD/Macromodel Simulation of Interconnected Digital Devices [p. 536]

S. Grivet-Talocia, I. Stievano, F. Canavero, and I. Maio

Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses [p. 542]

T. Lv, W. Wolf, J. Henkel, and H. Lekatsas

7A: System Level Simulation

Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer [p. 550]

S. Yoo, I. Bacivarov, A. Bouchhima, Y. Paviot, and A. Jerraya

Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation [p. 556]

W. Qin and S. Malik

Instruction Set Emulation for Rapid Prototyping of SoCs [p. 562]

J. Schnerr, G. Haug, and W. Rosenstiel

7B: Design Space Exploration for Reconfigurable Computing

Hardware/Software Design Space Exploration for a Reconfigurable Processor [p. 570]

A. La Rosa, L. Lavagno, and C. Passerone

From C Programs to the Configure-Execute Model [p. 576]

J. Cardoso and M. Weinhardt

FPGA-Based Implementation of a Serial RSA Processor [p. 582]

A. Mazzeo, L. Romano, G. Saggese, and N. Mazzocca

7C: On-Line Testing and Self-Repair

Optimal Reconfiguration Functions for Column or Data-Bit Built-In Self-Repair [p. 590]

M. Nicolaidis, N. Achouri, and S. Boutobza

Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric [p. 596]

P. Oikonomakos, M. Zwolinski, and B. Al-Hashimi

An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor [p. 602]

M. Rebaudengo, M. Sonza Reorda, and M. Violante

High Speed and Highly Testable Parallel Two -Rail Code Checker [p. 608]

M. Omaña, D. Rossi, and C. Metra

7E: Hot Topic: Safe Automotive Software Development (Embedded Software Forum)

Safe Automotive Software Development [p. 616]

K. Tindell, H. Kopetz, F. Wolf, and R. Ernst

7F: Mixed-Signal Design Techniques

Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits [p. 624]

P. Dobrovolný, G. Vandersteen, P. Wambacq, and S. Donnay

Linear Model-Based Error Identification and Calibration for Data Converters [p. 630]

C. Wegener and M. Kennedy

Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters [p. 636]

M. Albiol, J. González, and E. Alarcón

Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver [p. 642]

W. Eberle, H. De Man, G. Vandersteen, P. Wambacq, G. Gielen, and S. Donnay

8A: Design Space Exploration

Analytical Design Space Exploration of Caches for Embedded Systems [p. 650]

A. Ghosh and T. Givargis

Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs [p. 656]

V. Zivkovic, E. Deprettere, E. de Kock, and P. van der Wolf

Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform [p. 662]

L. Vanzago, J. Cambonie, B. Bhattacharya, and L. Lavagno

A First Step Towards HW/SW Partitioning of UML Specifications [p. 668]

W. Fornaciari, F. Salice, P. Micheli, and L. Zampella

Multi-Granularity Metrics for the Era of Strongly Personalized SOCs [p. 674]

Y. Le Moullec, J. Diguet, J. Philippe, N. Ben Amor, and M. Abid

8B: Low Power Architectures

Energy Estimation for Extensible Processors [p. 682]

Y. Fei, N. Jha, S. Ravi, and A. Raghunathan

Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures [p. 688]

J. Hu and R. Marculescu

Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface [p. 694]

W. Cheng and M. Pedram

MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters [p. 700]

H. Choo, K. Roy, and K. Muhammad

Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems [p. 706]

D. Bertozzi, L. Benini, A. Raghunathan, and S. Ravi

8C: System-on-Chip Testing

Low-Cost Software-Based Self-Testing of RISC Processor Cores [p. 714]

N. Kranitis, A. Paschalis, G. Xenoulis, D. Gizopoulos, and Y. Zorian

A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories [p. 720]

P. Bernardi, M. Rebaudengo, M. Sonza Reorda, and M. Violante

Test Data Compression: The System Integrator's Perspective [p. 726]

P. Gonciari, B. Al-Hashimi, and N. Nicolici

Time Domain Multiplexed TAM: Implementation and Comparison [p. 732]

Z. Ebadi and A. Ivanov

Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization [p. 738]

K. Goel and E. Marinissen

Delay Fault Testing of Core-Based Systems-On-A-Chip [p. 744]

Q. Xu and N. Nicolici

8D: Synthesis and Analysis of Digital Circuits

Reducing Multi-Valued Algebraic Operations to Binary [p. 752]

J. Jiang, R. Brayton, and A. Mishchenko

Combination of Lower Bounds in Exact BDD Minimization [p. 758]

R. Ebendt, W. Günther, and R. Drechsler

Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power Estimation [p. 764]

A. Freitas and A. Oliveira

Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information [p. 770]

U. Seidl, F. Johannes, and K. Eckl

8E: Embedded System Architectures (Embedded Software Forum)

Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology [p. 778]

A. Agarwal, T. Vijaykumar, and K. Roy

Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation [p. 784]

G. Surendra, S. Banerjee, and S. Nandy

On-Chip Stochastic Communication [p. 790]

T. Dumitras and R. Marculescu

An Integrated Approach for Improving Cache Behavior [p. 796]

G. Memik, A. Choudhary, M. Kandemir, and I. Kadayif

Rapid Configuration and Instruction Selection for an ASIP: A Case Study [p. 802]

N. Cheung, S. Parameswaran, and J. Henkel

8F: Specification and Verification in Action

Local Search for Boolean Relations on the Basis of Unit Propagation [p. 810]

Y. Novikov

Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis [p. 816]

A. Goel and R. Bryant

Efficient Preimage Computation Using a Novel Success-Driven ATPG [p. 822]

S. Sheng and M. Hsiao

Using Formal Techniques to Debug the AMBA System-On-Chip Bus Protocol [p. 828]

A. Roychoudhury, T. Mitra, and S. Karri

Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions [p. 834]

A. Ziv

9A: Hot Topic: RF Design Technology for Highly Integrated Communication Systems

Panel Statement [p. 842]

9B: Zoning Chip Estate

Power/Ground Mesh Area Optimization Using Multigrid-Based Technique [p. 850]

K. Wang and M. Marek-Sadowska

A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees [p. 856]

S. Wai, E. Young, and C. Chu

Crosstalk Reduction in Area Routing [p. 862]

R. Smey, P. Madden, and B. Swartz

Area Fill Generation with Inherent Data Volume Reduction [p. 868]

Y. Chen, A. Kahng, Y. Zheng, G. Robins, and A. Zelikovsky

9C: Panel: Transaction Based Design: Another Buzzword or the Solution to a Design Problem?

Panel Statement [p. 876]

9D: Trust in SAT-Based Verification?

Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and other Applications [p. 880]

L. Zhang and S. Malik

Verification of Proofs of Unsatisfiability for CNF Formulas [p. 886]

E. Goldberg and Y. Novikov

A Circuit SAT Solver with Signal Correlation Guided Learning [p. 892]

F. Lu, L. Wang, K. Cheng, and R. Huang

Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals [p. 898]

G. Cabodi, S. Nocco, and S. Quer

9E: Transformations for Real-Time Software (Embedded Software Forum)

Generalized Data Transformations for Enhancing Cache Behavior [p. 906]

V. De La Luz, M. Kandemir, I. Kadayif, and U. Sezer

Software Streaming via Block Streaming [p. 912]

P. Kuacharoen, V. Mooney, and V. Madisetti

Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems [p. 918]

Y. Zhang and K. Chakrabarty

9F1: Synthesis Tools for Asynchronous Circuits

Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design [p. 926]

A. Madalinski, A. Bystrov, V. Khomenko, and A. Yakovlev

STG Optimisation in the Direct Mapping of Asynchronous Circuits [p. 932]

D. Sokolov, A. Bystrov, and A. Yakovlev

9F2: Collaborative Design and WWW-Based Tools

Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues [p. 940]

L. Indrusiak, F. Lubitz, R. Reis, and M. Glesner

Dynamic Tool Integration in Heterogeneous Computer Networks [p. 946]

H. Eikerling, W. Mueller, T. Schattkowsky, and J. Wegner

10A: Performance Optimisation in Hardware/Software Codesign

Layered, Multi-Threaded, High-Level Performance Design [p. 954]

A. Cassidy, J. Paul, and D. Thomas

A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities [p. 960]

M. Schmitz, B. Al-Hashimi, and P. Eles

Processor/Memory Co-Exploration on Multiple Abstraction Levels [p. 966]

G. Braun, A. Wieferink, O. Schliebusch, R. Leupers, and H. Meyr, and A. Nohl

10B: Dynamic Resource Management for Reconfigurable Systems

Run-Time Management of Logic Resources on Reconfigurable Systems [p. 974]

M. Gericota, G. Alves, M. Silva, and J. Ferreira

Managing a Reconfigurable Processor in a General Purpose Workstation Environment [p. 980]

M. Dales

Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-On-Chip [p. 986]

J. Mignolet, V. Nollet, P. Coene, S. Vernalde, D. Verkest, and R. Lauwereins

10C: Advances in Test Pattern Generation

RTL Test Pattern Generation for High Quality Loosely Deterministic BIST [p. 994]

M. Santos, J. Fernandes, I. Teixeira, and J. Teixeira

A New Approach to Test Generation and Test Compaction for Scan Circuits [p. 1000]

I. Pomeranz and S. Reddy

Fully Automatic Test Program Generation for Microprocessor Cores [p. 1006]

F. Corno, G. Cumani, M. Sonza Reorda, and G. Squillero

On the Characterization of Hard-To-Detect Bridging Faults [p. 1012]

I. Pomeranz, S. Reddy, and S. Kundu

10D: Analogue and Digital Simulation

The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method [p. 1020]

Y. Lee and C. Chen

Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching [p. 1026]

Z. Wang and J. Zhu

A Fast Algorithm for the Layout Based Electro-Thermal Simulation [p. 1032]

M. Rencz, V. Székely, and A. Poppe

Platform Based Testbench Generation [p. 1038]

R. Henftling, M. Bauer, M. Zambaldi, A. Zinn, and W. Ecker

10E: Low Power Software (Embedded Software Forum)

Software Architectural Transformations: A New Approach to Low Energy Embedded Software [p. 1046]

T. Tan, A. Raghunathan, and N. Jha

Dynamic Functional Unit Assignment for Low Power [p. 1052]

S. Haga, N. Reeves, R. Barua, and D. Marculescu

Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy [p. 1058]

M. Kandemir, W. Zhang, and I. Kolcu

Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors [p. 1064]

D. Nicolaescu, A. Veidenbaum, and A. Nicolau

10F: Application Specific Memory Synthesis

Layer Assignment Techniques for Low Energy in Multi-Layered Memory Organisations [p. 1070]

E. Brockmeyer, M. Miranda, F. Catthoor, and H. Corporaal

Mesh Partitioning Approach to Energy Efficient Data Layout [p. 1076]

S. Hettiaratchi and P. Cheung

On-Chip Stack Based Memory Organization for Low Power Embedded Architectures [p. 1082]

M. Mamidipaka and N. Dutt

Poster Sessions

4P: CAD for Analogue Design, Design Methodologies and Physical Design

Figure of Merit Based Selection of A/D Converters [p. 1190]

M. Vogels and G. Gielen

XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines [p. 1092]

O. Kraus and M. Padeffke

Multithreaded Synchronous Data Flow Simulation [p. 1094]

J. Kin and J. Pino

PLFire: A Visualization Tool for Asynchronous Phased Logic Designs [p. 1096]

K. Fazel, M. Thornton, and R. Reese

Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering [p. 1098]

S. Doboli, G. Gothoskar, and A. Doboli

Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology [p. 1100]

A. Deb, J. Öberg, and A. Jantsch

A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs [p. 1102]

J. Lo, W. Kuo, T. Hwang, and A. Wu

Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration [p. 1104]

W. Choi and K. Bazargan

LIT -- An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks [p. 1106]

A. Girardi and S. Bampi

Symbolic Analysis of Nonlinear Analog Circuits [p. 1108]

A. Manthe, Z. Li, R. Shi, and K. Mayaram

Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects [p. 1110]

J. Gerling, O. Stübbe, J. Schrage, G. Mrozynski, and J. Teich

A New Crosstalk Noise Model for DOMINO Logic Circuits [p. 1112]

S. Choi and K. Roy

Modeling Noise Transfer Characteristic of Dynamic Logic Gates [p. 1114]

L. Ding and P. Mazumder

5P: Reconfigurable Computing and Systems Design

Heterogeneous Programmable Logic Block Architectures [p. 1118]

A. Koorapaty, V. Chandra, K. Tong, C. Patel, L. Pileggi, and H. Schmit

An Industrial/Academic Configurable System-On-Chip Project (CSoC): Coarse-Grain XPP-/Leon-Based Architecture Integration [p. 1120]

J. Becker, A. Thomas, M. Vorbach, and V. Baumgarte

Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs [p. 1122]

F. Moraes, D. Mesquita, J. Palma, L. Möller, and N. Calazans

Mapping Applications to an FPFA Tile [p. 1124]

M. Rosien, Y. Guo, G. Smit, and T. Krol

Load Distribution with the Proximity Congestion Awareness in a Network On Chip [p. 1126]

E. Nilsson, M. Millberg, J. Öberg, and A. Jantsch

Micro-Network for SoC: Implementation of a 32-Port SPIN Network [p. 1128]

A. Andriahantenaina and A. Greiner

A Fully Self-Timed Bit-Serial Pipeline-Architecture for Embedded Systems [p. 1130]

A. Rettberg, M. Zanella, C. Bobda, and T. Lehmann

Library Functions Timing Characterization for Source-Level Analysis [p. 1132]

C. Brandolese, W. Fornaciari, F. Salice, and D. Sciuto

G-MAC: An Application-Specific MAC/Co-Processor Synthesizer [p. 1134]

A. Chang, W. Kuo, T. Hwang, and A. Wu

Power Constrained High-Level Synthesis of Battery Powered Systems [p. 1136]

S. Nielsen and J. Madsen

PARLAK: Parametrized Lock Cache Generator [p. 1138]

B. Akgul and V. Mooney

A Secure Web-Based Framework for Electronic System Level Design [p. 1140]

T. Kazmierski and X. Yang

6P: Low Power Design and Estimation, Verification and Testing

Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor [p. 1144]

P. Op de Beeck, C. Ghez, E. Brockmeyer, M. Miranda, F. Catthoor, and G. Deconinck

Compiler Support for Reducing Leakage Energy Consumption [p. 1146]

W. Zhang, M. Kandemir, N. Vijaykrishnan, M. Irwin, and V. De

An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries [p. 1148]

P. Rong and M. Pedram

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems [p. 1150]

J. Luo, N. Jha, and L. Peh

Decomposition of Extended Finite State Machine for Low Power Design [p. 1152]

M. Lee, T. Hwang, and S. Huang

Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations [p. 1154]

N. Yevtushenko, T. Villa, R. Brayton, A. Sangiovanni-Vincentelli, and A. Petrenko

Using RTL Statespace Information and State Encoding for Induction Based Property Checking [p. 1156]

M. Wedler, D. Stoffel, and W. Kunz

Combining Simulation and Guided Traversal for the Verification of Concurrent Systems [p. 1158]

E. Pastor and M. Peña

Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies [p. 1160]

N. Sirisantana and K. Roy

Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes [p. 1162]

S. Tarnick

Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees [p. 1164]

P. Drineas and Y. Makris

7P: System Level Design and Specification and Testing Techniques

SAT-Based Techniques in System Synthesis [p. 1168]

C. Haubelt, J. Teich, R. Feldmann, and B. Monien

Refinement of Mixed-Signal Systems with SystemC [p. 1170]

C. Grimm, C. Meise, W. Heupke, and K. Waldschmidt

Polychrony for Refinement-Based Design [p. 1172]

J. Talpin, P. Le Guernic, S. Shukla, R. Gupta, and F. Doucet

Automatic Generation of Simulation Monitors from Quantitative Constraint Formula [p. 1174]

X. Chen, H. Hsieh, F. Balarin, and Y. Watanabe

Consequences of RAM Bitline Twisting for Test Coverage [p. 1176]

I. Schanstra and J. van de Goor

An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme [p. 1178]

F. Corsi, C. Marzocca, and G. Matarrese

Test Generation for Acyclic Sequential Circuits with Single Stuck-At Fault Combinational ATPG [p. 1180]

H. Ichihara and T. Inoue

Comparison of Test Pattern Decompression Techniques [p. 1182]

O. Novák

Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST [p. 1184]

I. Polian, B. Becker, and S. Reddy

Test Data Compression Based on Output Dependence [p. 1186]

I. Pomeranz and S. Reddy

A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization [p. [p. 1188]

V. Iyengar, A. Chandra, S. Schweizer, and K. Chakrabarty